Abstract: A programmable logic device including a plurality of programmable atomic logic elements (PALEs) where each PALE has a plurality of data inputs and generates a data output signal. The PALEs are logically arranged as a plurality of hierarchically coupled partitions. Each partition is defined by a unique set of the next lower hierarchy partitions and an interconnect bus that extends only to the unique set of the next lower partitions that are within that partition. The lowest level of hierarchy is one of the plurality of PALEs. A plurality of hyperlinks provided within each PALE programmably couples the PALE data output signal to each of the interconnect busses in each of the higher levels of hierarchy that include the PALE. Preferably, the PALE also includes a tunnel connection for coupling the PALE data output signal to adjacent neighbor PALEs without using the interconnect bus of any of the partitions.

Abstract: A multi-chip module including a multi-layer substrate and a patterned metallization layer formed on each layer of the substrate. A multi-tiered cavity is formed with an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity. A plurality of ICs are mounted on the IC mounting surface of the cavity. A first set of wire bonds extends from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity. A second set of wire bonds extends from the at least one IC to bond pads of an adjacent IC. A third set of wire bonds extends from the at least one IC to bond pads of the adjacent IC such that the third set of wire bonds has a higher loop height than the second set of wire bonds.

Abstract: An analog electronic test probe includes hundreds of inputs each connected to two amplifiers, each in a separate multiplexer stage on an integrated circuit. A programmer, responsive to a dial, shifts data through a shift register of latches each of which is connected to one of the amplifiers, activating the amplifier(s) connected to the selected input, thereby multiplexing it (them) to selected output(s). Similarly, the gain for each output may be selected. An outdisable circuit connected to the outputs of each multiplexer and the outputs of each IC chip causes each output to appear electrically as an open circuit when no input associated with the multiplexer or chip is selected. This permits any number of multiplexers and IC chips to be daisy-chained together.

Abstract: Disclosed is an analog to digital conversion system that converts high speed analog signals to digital values without using a hold circuit. The system has a narrow aperture sampling circuit that samples an input signal and feeds the sampled signal to a capacitor. A resistor in parallel with the capacitor discharges the capacitor at a predetermined rate, thus the capacitor does not hold the sampled signal. The discharging signal output of the capacitor-resistor circuit is amplified and then filtered using a low-pass filter, which has essentially linear phase shift and no undershoot. The filtered signal is then amplified and fed to a flash analog to digital converter which converts the signal into a digital value. The low-pass filter creates a Gaussian output and the converter is timed to convert the signal at the peak of the filter output.

Abstract: A probe apparatus for use with analyzing devices, primarily oscilloscopes, which uses pole-zero cancellation to provide a probe with low capacitance and wide bandwidth. Pole-zero cancellation enables the probe to have constant gain at all frequencies. In one embodiment, the coaxial cable between the probe tip and the replication amplifier is terminated in its characteristic impedance to provide constant gain at all frequencies regardless of cable length. Use of pole-zero cancellation and thick film technology enables building a probe with a small, durable tip.