Abstract: Among the embodiments of the present invention, is memory control circuitry (40) that includes a detection circuit (44) and a monostable multivibrator (104). This detection circuit (40) is responsive to a transition of a number of address inputs to generate a trigger signal. The monostable multivibrator (104) is responsive to the trigger signal to change a memory control output signal from a first state to a second state. The monostable multivibrator (40) is further responsive to a memory interlock input signal to change the memory control output signal from the second state to the first state. The memory control circuitry (40) can be coupled to drive a clock input of a synchronous memory (30) to provide for asynchronous operation thereof.

Abstract: Disclosed are methods and apparatus for providing a relational operation with a content addressable memory (24). One form includes providing a multibit input to a content addressable memory location (30) and generating a relational state bit output corresponding to an arithmetic relationship between the input and the memory location (30). A first bit of the input or a complement of it is routed to the output if the first bit and most significant bit of the location are unequal. If the first bit and the most significant bit are equal, a second bit of the input or its complement is routed to the output if the second bit and next most significant bit of the location are unequal. A relational logic circuit (52) is included for each memory cell (40) of the location (30) to provide the relational operation.

Abstract: A redundant memory system includes an address bus, a random access memory, a content addressable memory, a replacement memory, and a data bus. The random access memory includes a number of addressable memory locations each accessed by a different one of a number of addresses provided by the address bus. The content addressable memory stores a number of defective location addresses each corresponding to a defective addressable memory location of the random access memory and responds to a match between an address provided by the address bus and one of the defective location addresses to activate one of a number of match lines. The replacement memory is coupled to the content addressable memory by the match lines and includes a number of replacement memory locations each accessed by activating a different one of the lines.

Abstract: Disclosed are methods and apparatus for providing a relational operation with a content addressable memory (24). One form includes providing a multibit input to a content addressable memory location (30) and generating a relational state bit output corresponding to an arithmetic relationship between the input and the memory location (30). A first bit of the input or a complement of it is routed to the output if the first bit and most significant bit of the location are unequal. If the first bit and the most significant bit are equal, a second bit of the input or its complement is routed to the output if the second bit and next most significant bit of the location are unequal. A relational logic circuit (52) is included for each memory cell (40) of the location (30) to provide the relational operation.

Abstract: Among the embodiments of the present invention, is memory control circuitry (40) that includes a detection circuit (44) and a monostable multivibrator (104). This detection circuit (40) is responsive to a transition of a number of address inputs to generate a trigger signal. The monostable multivibrator (104) is responsive to the trigger signal to change a memory control output signal from a first state to a second state. The monostable multivibrator (40) is further responsive to a memory interlock input signal to change the memory control output signal from the second state to the first state. The memory control circuitry (40) can be coupled to drive a clock input of a synchronous memory (30) to provide for asynchronous operation thereof.

Abstract: This disclosure sets forth the use of input 2-bit encoders to form an encoder network capable of handling any number of encoder inputs by using the VALID output of each input 2-bit encoder as a data input to a later stage encoder and to select 2-way selector circuits using the code outputs of the input 2-bit encoders for selection of highest match.This is accomplished through the use of first and second input 2.sup.n encoders, the first being provided with the 2.sup.n high order inputs and the second being supplied with the 2.sup.n low order inputs and the outputs of the input encoders being coupled to a single 2-input encoder and n 2-way selectors to provide an encoder network with fewer circuits and better performance due to fewer stages of delay.If the number of desired inputs to the network is less than 2.sup.n but greater than 2.sup.n-1, known logic reduction techniques may be applied to the next higher 2.sup.n input encoder network to implement the desired 2.sup.n-1 encoder network.

Abstract: A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor arranged in series with a second or pull-up P-channel transistor and a third P-channel transistor connected from the common point between the first and second transistors and the gate electrode of the first transistor. The first and second transistors are disposed between a data output terminal and a first voltage source having a supply voltage of a given magnitude, with the data output terminal also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor, disposed in a common N-well with the other P-channel transistors, is connected at its source to the first voltage source and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.

Abstract: A memory system includes a data storage matrix having columns and rows and a redundant storage matrix having at least one column. The columns of the storage matrix are addressed by column addresses each defining a logical column address for a data bit of a row and corresponding to a predetermined physical column of the storage matrix. The storage matrix is readable in parallel, the parallel read data being serially presented to an output port in a sequence determined by the physical order of the columns of the storage matrix. Column redundancy logic, response to a column address corresponding to a defective physical column of the storage matrix, stores a data bit in a column of the redundant storage matrix. Redundancy control logic response to the column redundancy logic operates on data parallel read from the storage matrix by column addressing, to insert the data bit stored in the redundant column between the data bits read from the data storage matrix according to its logical column address.