Abstract: Parallel chromatography systems and continuous manufacturing methods are described herein that utilize two or more chromatography column skids having columns operating in parallel with automation controls governing which column to load at a given time.

Abstract: In one embodiment, a method includes: receiving, in an edge platform, a plurality of messages from a plurality of edge devices coupled to the edge platform, the plurality of messages comprising metadata including priority information and granularity information; extracting at least the priority information from the plurality of messages; storing the plurality of messages in entries of a pending request queue according to the priority information; selecting a first message stored in the pending request queue for delivery to a destination circuit; and sending a message header for the first message to the destination circuit via at least one interface circuit, the message header including the priority information, and thereafter sending a plurality of packets including payload information of the first message to the destination circuit via the at least one interface circuit. Other embodiments are described and claimed.

Abstract: Parallel chromatography systems and continuous manufacturing methods are described herein that utilize two or more chromatography column skids having columns operating in parallel with automation controls governing which column to load at a given time.

Abstract: A tubing support device for tubing of a drug manufacturing system. The tubing support device has a body having a first end, a second end, and a plurality of projections. The plurality of projections include a first projection disposed at the first end and a second projection disposed at the second end. Each of the first and second projections includes an aperture adapted to receive a fastener. A bore extends from the first end to the second end of the body, and the bore is adapted to receive welded tubing such that the body reinforces the tubing, allowing the tubing to contain fluids at high pressures and/or preventing kinking in the tubing.

Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.

Abstract: Embodiments include a waveguide bundle, a dielectric waveguide, and a vehicle. The waveguide bundle includes dielectric waveguides, where each dielectric waveguide has a dielectric core and a conductive coating around the dielectric core. The waveguide bundle also has a power delivery layer formed around the dielectric waveguides, and an insulating jacket enclosing the waveguide bundle. The waveguide bundle may also include the power deliver layer as a braided shield, where the braided shield provides at least one of a DC and an AC power line. The waveguide bundle may further have one of the dielectric waveguides provide a DC ground over their conductive coatings, where the AC power line does not use the braided shield as reference or ground. The waveguide bundle may include that the power delivery layer is separated from the dielectric waveguides by a braided shield, where the power delivery layer is a power delivery braided foil.

Abstract: A biologics manufacturing process that connects the drug substance and drug product processes into an integrated, continuous process.

Abstract: In one embodiment, a method includes: receiving, in an edge platform, a plurality of messages from a plurality of edge devices coupled to the edge platform, the plurality of messages comprising metadata including priority information and granularity information; extracting at least the priority information from the plurality of messages; storing the plurality of messages in entries of a pending request queue according to the priority information; selecting a first message stored in the pending request queue for delivery to a destination circuit; and sending a message header for the first message to the destination circuit via at least one interface circuit, the message header including the priority information, and thereafter sending a plurality of packets including payload information of the first message to the destination circuit via the at least one interface circuit. Other embodiments are described and claimed.

Abstract: Embodiments include a waveguide bundle, a dielectric waveguide, and a vehicle. The waveguide bundle includes dielectric waveguides, where each dielectric waveguide has a dielectric core and a conductive coating around the dielectric core. The waveguide bundle also has a power delivery layer formed around the dielectric waveguides, and an insulating jacket enclosing the waveguide bundle. The waveguide bundle may also include the power deliver layer as a braided shield, where the braided shield provides at least one of a DC and an AC power line. The waveguide bundle may further have one of the dielectric waveguides provide a DC ground over their conductive coatings, where the AC power line does not use the braided shield as reference or ground. The waveguide bundle may include that the power delivery layer is separated from the dielectric waveguides by a braided shield, where the power delivery layer is a power delivery braided foil.

Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract: A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

Abstract: Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.

Abstract: Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misalignment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract: Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract: Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack.

Abstract: Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank.

Abstract: A stacked memory allowing variance in device interconnects. An embodiment of a memory device includes a system element for the memory device, the system element including multiple pads, and a memory stack connected with the system element, the memory stack having one or more memory die layers, a connection of the system element and the memory stack including interconnects for connecting a first memory die layer and the plurality of pads of the system element. For a single memory die layer in the memory stack, a first subset of the plurality of pads is utilized for a first group of interconnects for the connection of the system element and the memory stack, and for two or more memory die layers, the first subset and an additional second subset of the plurality of pads are utilized for the first group of interconnects and a second group of interconnects for the connection of the system element and the memory stack.

Abstract: Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.