Abstract: The present disclosure provides a computer-implemented method, which includes receiving a dispute information pertaining to a billing dispute by a processor, from a device associated with a customer. The method includes computing, by the processor, a score based on the dispute information, for determining validity of the billing dispute. The billing dispute is categorized based on the score computed for the dispute information. One or more actions are subsequently presented to one or more parties associated with the dispute information for resolving the billing dispute. The processor is also configured to prioritize the one or more actions based on the score computed. The present disclosure also provides a system capable of implementing the aforesaid method for prioritizing and resolving the billing disputes in an automated manner.

Abstract: Methods and systems for assessing performance and risk in financing supply chain are disclosed. The method includes accessing a behavioral data of an entity. The behavioral data comprises at least one of a primary data and a secondary data. The primary data is associated with one or more assets of the entity and comprises historical transaction data of the entity with financial institutions. The secondary data is sourced from an external system and comprises at least a credit information and a business transaction information of the entity. The method also includes generating a unified model for the entity based on the behavioral data of the entity. The method includes predicting a plurality of risk metrics based on the unified model using one or more machine learning models, and determining a credit rating of the entity based on the plurality of risk metrics and a confidence measure.

Abstract: Embodiments provide methods and systems for generating a plain-text explanation for a prediction score associated with a record. An explanation generation system is configured to receive the record from a user. A prediction score is calculated using an ML model and a plurality of feature variables that are contributing to the prediction score are determined by the system. The plurality of feature variables are rank-ordered by the system based on their corresponding contribution to the prediction score. Further, correlated features are determined from among the plurality of feature variables and are grouped into one or more groups of correlated feature variables. At least one feature variable from each of the one or more groups is selected to determine a list of feature variables. The list of feature variables is passed to a sentence creation module that generates a plain-text explanation. The generated plain-text explanation is displayed to the user.

Abstract: The present disclosure provides a computer-implemented method, which includes receiving a dispute information pertaining to a billing dispute by a processor, from a device associated with a customer. The method includes computing, by the processor, a score based on the dispute information, for determining validity of the billing dispute. The billing dispute is categorized based on the score computed for the dispute information. One or more actions are subsequently presented to one or more parties associated with the dispute information for resolving the billing dispute. The processor is also configured to prioritize the one or more actions based on the score computed. The present disclosure also provides a system capable of implementing the aforesaid method for prioritizing and resolving the billing disputes in an automated manner.

Abstract: Methods and systems for assessing performance and risk in financing supply chain are disclosed. The method includes accessing a behavioral data of an entity. The behavioral data comprises at least one of a primary data and a secondary data. The primary data is associated with one or more assets of the entity and comprises historical transaction data of the entity with financial institutions. The secondary data is sourced from an external system and comprises at least a credit information and a business transaction information of the entity. The method also includes generating a unified model for the entity based on the behavioral data of the entity. The method includes predicting a plurality of risk metrics based on the unified model using one or more machine learning models, and determining a credit rating of the entity based on the plurality of risk metrics and a confidence measure.

Abstract: A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.

Abstract: The preferred embodiments described below provide a method and memory device for improving the precision of a temperature-sensor circuit. In one preferred embodiment, first and second temperature-dependent reference voltages are generated and compared, and an operating condition of the memory array is controlled based on the result of the comparison. Instead of using a temperature-dependent reference voltage, a temperature-dependent reference current can be used. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: The preferred embodiments described below provide a method and memory device for improving the precision of a temperature-sensor circuit. In one preferred embodiment, first and second temperature-dependent reference voltages are generated and compared, and an operating condition of the memory array is controlled based on the result of the comparison. Instead of using a temperature-dependent reference voltage, a temperature-dependent reference current can be used. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract: Methods and apparatus are described for dynamically controlling a charge pump system including a plurality of charge pump stages, with each charge pump stage coupled between an input voltage VIN at an input voltage node and an output voltage VOUT at an output voltage node. In particular, the configuration of the charge pump stages may be dynamically controlled during a transition on VOUT from a first voltage to a second voltage to improve the circuit's transient response.

Abstract: A memory array comprising array lines of first and second types coupled to memory cells includes a first hierarchical decoder circuit for decoding address information and selecting one or more array lines of the first type. The first hierarchical decoder circuit includes at least two hierarchical levels of multi-headed decoder circuits. The first hierarchical decoder circuit may include a first-level decoder circuit for decoding a plurality of address signal inputs and generating a plurality of first-level decoded outputs, a plurality of second-level multi-headed decoder circuits, each respective one coupled to a respective first-level decoded output, each for providing a respective plurality of second-level decoded outputs, and a plurality of third-level multi-headed decoder circuits, each respective one coupled to a respective second-level decoded output, each for providing a respective plurality of third-level decoded outputs coupled to the memory array.

Abstract: In an embodiment of the invention an integrated circuit includes a memory array having a first plurality of decoded lines traversing across the memory array and a pair of dual-mode decoders, each decoder coupled to each of the plurality of decoded lines a respective location along said decoded lines, such as at opposite ends thereof. Both decoder circuits receive like address information. Normally both decoder circuits operate in a forward decode mode to decode the address information and drive a selected one of the decoded lines. During a test mode, one decoder is enabled in a reverse decode mode while the other decoder remains in a forward decode mode to verify proper decode operation and integrity of the decoded lines between the decoders.

Abstract: An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell's location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.

Abstract: The preferred embodiments described herein relate to a method and system for temperature compensation for memory cells with temperature-dependent behavior. In one preferred embodiment, at least one of a first temperature-dependent reference voltage comprising a negative temperature coefficient and a second temperature-dependent reference voltage comprising a positive temperature coefficient is generated. One of a wordline voltage and a bitline voltage is generated from one of the at least one of the first and second temperature-dependent reference voltages. The other of the wordline and bitline voltages is generated, and the wordline and bitline voltages are applied across a memory cell. Other methods and systems are disclosed for sensing a memory cell comprising temperature-dependent behavior, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: The preferred embodiments described herein relate to a method and system for temperature compensation for memory cells with temperature-dependent behavior. In one preferred embodiment, at least one of a first temperature-dependent reference voltage comprising a negative temperature coefficient and a second temperature-dependent reference voltage comprising a positive temperature coefficient is generated. One of a wordline voltage and a bitline voltage is generated from one of the at least one of the first and second temperature-dependent reference voltages. The other of the wordline and bitline voltages is generated, and the wordline and bitline voltages are applied across a memory cell. Other methods and systems are disclosed for sensing a memory cell comprising temperature-dependent behavior, and each of the preferred embodiments can be used alone or in combination with one another.