Abstract: A switched current source circuit, comprising first and second voltage source nodes; a load; a current source; and capacitor switching circuitry comprising a load node, a capacitor and a plurality of switches configured, based on a control signal, to adopt a biasing configuration followed by an active configuration, wherein in the biasing configuration, the load node is conductively connected to the second voltage source node to bias a voltage level at the load node, and the capacitor is connected so that it at least partly charges; and in the active configuration, the load node is conductively connected via the load to the first voltage source node, and via the capacitor to the current source to increase a potential difference between the first voltage source node and the load node.

Abstract: A comparator including: first and second input transistors connected to control signals at first and second nodes of the comparator; latch circuitry; at least one controllable offset-correction component having an input terminal and connected to control the signal at one of the first and second nodes based on an offset-correction signal provided at its input terminal; for each controllable offset-correction component, an offset correction circuit configured to provide the offset-correction signal provided at its input terminal; and control circuitry.

Abstract: Mixed-signal circuitry including a set of capacitive digital-to-analogue converter, CDAC, units for carrying out digital-to-analogue conversion operations to convert respective digital values into corresponding analogue values; and control circuitry, where: each CDAC unit includes an array of capacitors at least some of which are configured to be individually-switched dependent on the digital values, the capacitors configured to have nominal capacitances; a given capacitor of the array of capacitors in each of the CDAC units is a target capacitor; the set of CDAC units includes a plurality of sub-sets of CDAC units; at least one of the target capacitors per sub-set of CDAC units is a variable capacitor, controllable by the control circuitry to have any one of a plurality of nominal capacitances defined by the configuration of that capacitor.

Abstract: Analogue-to-digital converter, ADC, circuitry, including: an analogue input terminal; a comparator having first and second comparator-input terminals; and successive-approximation control circuitry to apply a potential difference across the first and second comparator-input terminals based on an input voltage signal, and to control the potential difference for a series of successive approximation operations to cause the comparator to test in each successive approximation operation whether a magnitude of an analogue input voltage signal is larger or smaller than a corresponding test value, the test value for each successive approximation operation being, dependent on a comparison result generated by the comparator in the preceding approximation operation, bigger or smaller than the test value for the preceding approximation operation by a difference amount configured for that successive approximation operation.

Abstract: A controllable reactance implemented within an integrated circuit includes a first sub-circuit (20) comprising a reactive element, for example a capacitor 12, coupled in series with a transistor (14). A controllable current source (16) injects a controllable bias current through the transistor (14) to vary the effective resistance of the transistor (14) and hence the effective complex impedance of the capacitor combination. A second transistor (18) amplifies the current to increase the effective capacitance. Preferably, a second sub-circuit (24) includes corresponding components (26, 28, 30) to mirror the real component of the current flowing in the first sub-circuit (20), and transistors (32 and 34) to reflect an inverse current to the coupling node line (22) to cancel the real component of the current at the node, to thus simulate a purely capacitive circuit. An oscillator embodying this circuit is also disclosed.

Abstract: A driver circuit has first and second output drivers, monitor circuitry for deriving control signals related to driven signal levels, and supply circuitry responsive to the control signals for controlling the supply voltage to the output drivers. The monitor circuitry can be connected to monitor the voltage at the supply inputs of the output drivers for deriving the control signals. Alternatively, the monitor circuitry can be connected directly to monitor driven output levels from the drivers. In the latter case, the output levels to be monitored are rectified. The monitor circuitry can comprise first and second operational amplifiers for comparing a monitored voltage from first and second output drivers, respectively, to a first and second reference voltages, respectively. The supply circuitry can comprise first and second constant current sources, for example field effect transistors.

Abstract: A differential output circuit has first and second output lines and an output impedance connected between the first and second lines. The output impedance includes an active device (e.g., a field effect transistor) having a control input for receiving a control signal value for controlling the impedance value of the active device. A bias circuit is responsive to a reference impedance element for generating the control signal value for controlling the impedance value of the active device. An output driver stage is connected to the first and second output lines for supplying first and second differential driven output signals to the first and second output lines, respectively. An integrated circuit can include a number of differential output circuits and a common bias circuit responsive to a single reference impedance element for generating the control signal value for controlling the impedance value of each active device.

Abstract: A differential signal receiver circuit includes a first differential stage receiving input differential signals, a second differential stage receiving shifted differential signals and summing stage summing outputs of the first and second differential stages. Preferably the summing stage is formed by a wired-OR connection between the first and second differential stage outputs. The circuit finds application in digital systems for receiving data transmitted between digital equipment.

Abstract: A voltage comparator circuit includes a comparator 42 having a first comparison input, a second comparison input and first and second switched current memories 52, 58 (e.g., switched FETs) connectable, respectively, to the first and second comparator inputs for input voltage offset compensation. In use, during a storage phase, a current value is stored in the switched current memory for each of the first and second comparison inputs and, during a comparison phase, the stored current values are used to compensate for voltage offsets between the comparison inputs.

Abstract: A differential delay buffer includes a variable delay buffer unit, the variable delay buffer unit having a differential stage followed by a variable hysteresis stage. A plurality of variable delay buffer units can be cascaded together, in each variable delay buffer units a part of the required delay being effected. The variable hysteresis stage is responsive to the signal level at a second differential stage output to recover the signal at a first differential signal output from the variable delay buffer unit and is responsive to the signal level at a first differential stage output to recover the signal at the second delayed differential signal output for the variable delay buffer unit. The differential delay buffer can be included in a delay locked loop in data transmission applications.

Abstract: A differential signal receiver circuit includes a first differential stage receiving input differential signals, a second differential stage receiving shifted differential signals and summing stage summing outputs of the first and second differential stages. Preferably the summing stage is formed by a wired-OR connection between the first and second differential stage outputs. The circuit finds application in digital systems for receiving data transmitted between digital equipment.

Abstract: An analog to digital converter has an analog signal input, reference voltage divider and a plurality of comparators. Each comparator has a first input connected to said analog signal input and a reference input connected to receive a respective predetermined reference voltage from the reference voltage divider. In addition, test mode circuitry is provided for feeding a sequence of test voltages from the voltage divider to the first input of the comparators in a test mode. A decoder is connected to an output of each comparator for generating a binary output signal representative of an input analog signal.