Abstract: An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.

Abstract: An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.

Abstract: Any number of transceiver channels is tested for jitter generation/tolerance simultaneously. Tested channels use a serial loopback path to connect a transceiver transmit channel to a transceiver receiver channel. Both the transmitter and receiver PLLs are connected to a common reference clock. The reference clock is modulated with jitter at a frequency below the bandwidth of the transmitter PLL but above the bandwidth of the receiver PLL. The magnitude of eye closure (in an eye diagram), which is equivalent to the amplitude of the jitter, is used to filter out bad transceiver units.

Abstract: A programmable logic device that receives and stores configuration data in configurable random-access-memory has differential signal input buffer circuitry for receiving the configuration data from a configuration device in differential signal form at high speeds. The programmable logic device may have clock and data recovery circuitry that receives a reference clock and that generates a corresponding internal clock that is used for receiving the configuration data. Error detection circuitry may be used to detect errors occurring during data transmission. The configuration device may have a serializer that serializes parallel configuration data received from memory and differential signal output driver circuitry that provides the configuration data in differential signal form to the programmable logic device.

Abstract: Any number of transceiver channels is tested for jitter generation/tolerance simultaneously. Tested channels use a serial loopback path to connect a transceiver transmit channel to a transceiver receiver channel. Both the transmitter and receiver PLLs are connected to a common reference clock. The reference clock is modulated with jitter at a frequency below the bandwidth of the transmitter PLL but above the bandwidth of the receiver PLL. The magnitude of eye closure (in an eye diagram), which is equivalent to the amplitude of the jitter, is used to filter out bad transceiver units.