Patents by Inventor Kenneth T. Daxer

Kenneth T. Daxer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11281195
    Abstract: An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Kenneth T. Daxer, Gregory Steinke, Adam J. Wright, Kalyana Ravindra Kantipudi
  • Publication number: 20190101906
    Abstract: An integrated circuit may include an embedded test processor that is capable of performing in-field testing and repair of hardware-related defects without having to remove the integrated circuit from the customer's board. The test processor can be used to drive and monitor test vectors to performing defect screening on input-output circuitry, logic circuitry including lookup table (LUT) circuits and digital signal processing (DSP) circuits, transceiver circuitry, and configuration random-access memory circuitry. The test processor can generate a failure mechanism report and selectively fix repairable defects via a hardware redundancy scheme. The failure mechanism report allows the customer to identify the root cause of failure in the overall system.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventors: Kenneth T. Daxer, Gregory Steinke, Adam J. Wright, Kalyana Ravindra Kantipudi
  • Patent number: 7936809
    Abstract: Any number of transceiver channels is tested for jitter generation/tolerance simultaneously. Tested channels use a serial loopback path to connect a transceiver transmit channel to a transceiver receiver channel. Both the transmitter and receiver PLLs are connected to a common reference clock. The reference clock is modulated with jitter at a frequency below the bandwidth of the transmitter PLL but above the bandwidth of the receiver PLL. The magnitude of eye closure (in an eye diagram), which is equivalent to the amplitude of the jitter, is used to filter out bad transceiver units.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: May 3, 2011
    Assignee: Altera Corporation
    Inventors: Kenneth T. Daxer, Sergey Shumarayev
  • Patent number: 7795909
    Abstract: A programmable logic device that receives and stores configuration data in configurable random-access-memory has differential signal input buffer circuitry for receiving the configuration data from a configuration device in differential signal form at high speeds. The programmable logic device may have clock and data recovery circuitry that receives a reference clock and that generates a corresponding internal clock that is used for receiving the configuration data. Error detection circuitry may be used to detect errors occurring during data transmission. The configuration device may have a serializer that serializes parallel configuration data received from memory and differential signal output driver circuitry that provides the configuration data in differential signal form to the programmable logic device.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: September 14, 2010
    Assignee: Altera Corporation
    Inventors: Kenneth T. Daxer, Adam J. Wright
  • Publication number: 20080013609
    Abstract: Any number of transceiver channels is tested for jitter generation/tolerance simultaneously. Tested channels use a serial loopback path to connect a transceiver transmit channel to a transceiver receiver channel. Both the transmitter and receiver PLLs are connected to a common reference clock. The reference clock is modulated with jitter at a frequency below the bandwidth of the transmitter PLL but above the bandwidth of the receiver PLL. The magnitude of eye closure (in an eye diagram), which is equivalent to the amplitude of the jitter, is used to filter out bad transceiver units.
    Type: Application
    Filed: July 11, 2006
    Publication date: January 17, 2008
    Applicant: Altera Corporation
    Inventors: Kenneth T. Daxer, Sergey Shumarayev