Abstract: A chair back height adjustment mechanism for a chair having a chair back supporting standard and a chair back bracket with a chair back or backrest mounted thereon includes a rack gear on the chair back standard, a pinion gear supported in a bearing on the chair back bracket, a worm gear coaxial with the pinion gear, and worm threads on a dial shaft supported on the bracket. Rotation of the dial causes the worm member to rotate the worm gear and the pinion gear whereby the bracket supporting the pinion gear is translated in relation to the chair back standard. The chair back can only be adjusted by operation of the dial due to the nature of the worm and worm gear combination, thus preventing changes in the adjusted position of the chair back by contact with the chair back.

Abstract: In a data transmission system, for communicating messages between a base station and a plurality of mobile stations, each mobile station includes a radio frequency transceiver and a programmable data terminal for sending and receiving predeterminedly formatted digitally encoded messages. A keyboard subsystem and character display subsystem are controlled by a programmable microprocessor subsystem which also processes received and transmitted messages. A transmit and receive system clock interrupts the operation of the microcomputer to process messages. The messages include a cyclical redundant check byte as well as a control number byte. Characters which are not editable blink. A terminal status display line is provided and a message received character is also provided. The system sets the system clock period to be the same for all data rates. Automatic restart of the system is provided as well as a means for detecting and generating a pseudo-random message preamble.

Abstract: An addressing circuitry for a dot matrix vertical scan plasma display includes a character row counter and a character column counter, a random access memory, a dot pattern generator, a parallel to series shift register, and a driver for the display. The addressing circuitry is responsive to a processor. Alpha-numeric digital characters to be displayed are read out of the memory in sequence in response to a sequence signal from the character row counter and the character column signal output. The words read out of the memory are converted into dot matrix pattern by the dot pattern generator and displayed on the plasma display via the parallel to serial shift register and driver. An offset adder is used when the number of character rows and the number of characters per row of the display are other than binary progression numbers in generating a sequence signal. The offset adder is interposed between the random access memory and the row and column outputs.