Abstract: An output stage amplifier circuit in accordance with the present invention overcomes many shortcomings of the prior art. A output stage amplifier circuit for providing a high output voltage and current reference signal suitably includes an output buffer configured with a compensation circuit for reducing disturbances introduced into the output stage amplifier circuit by voltage supply rails, such as parasitic ringing and other disturbances. The compensation circuit can suitably comprise a first compensation device, such as at least one capacitor, and a second compensation device, such as at least one capacitor. The compensation devices are suitably coupled between an input terminal of the output stage amplifier circuit and a pair of transistors proximate a pair of output transistors of the output stage amplifier circuit, and are configured to provide “pole-zero” compensation to the output stage amplifier circuit.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A bias rail buffer circuit and method in accordance with the present invention overcomes many shortcomings of the prior art. A bias rail buffer circuit for providing a reference signal is suitably configured to absorb external disturbances appearing on an output reference signal. A method for absorbing the external disturbances appearing at the output reference signal suitably includes the use of complementary transistors to source current and sink current to said output reference signal, depending on whether the external disturbances are providing a decrease or an increase to the output reference signal. The bias rail buffer circuit suitably includes an input transistor, a first pair of complementary transistors and a second pair of complementary transistors, such that the second pair of complementary transistors operate to source current and sink current to absorb external disturbances imparted on said output reference signal.

Abstract: A current mirror circuit in accordance with the present invention overcomes many shortcomings of the prior art. A current mirror circuit for providing a current reference signal suitably includes at least one degeneration resistor to provide more degeneration for lower voltage noise while also including at least one clamping device to preventing saturation of the current mirror. The clamping device suitably comprises at least one diode, such as, for example, a Schottky-type diode. Moreover, the clamping device can be suitably configured to facilitate a higher slew rate of the current mirror circuit.

Abstract: A wideband operational amplifier in accordance with the present invention overcomes many shortcomings of the prior art. A wideband operational amplifier may be configured to provide a high output voltage and high output current. The amplifier may comprise an input stage having a first input buffer and a second input buffer, and an output stage amplifier having an output buffer. The input stage may also include current mirrors configured to facilitate a lower input offset voltage and lower input voltage noise. Moreover, the operational amplifier may also provide a wide common-mode input range and full power bandwidth simultaneously.

Abstract: A compensation circuit in a high speed integrated circuit operational amplifier that includes an input stage having first and second outputs connected to emitters of first and second PNP cascode transistors. A base of an NPN cascode transistor is coupled to a collector of the first PNP cascode transistor. A resistor circuit is connected between the collectors of the second PNP cascode transistor and the NPN cascode transistor. First and second inputs of a diamond follower output buffer are connected to the collectors of the NPN cascode transistor and second PNP cascode transistor, respectively. A compensation circuit includes first and second compensation capacitors connected to the collectors of the NPN cascode transistor and the second PNP cascode transistor, respectively, to prevent instability of an output voltage of the diamond follower buffer circuit.

Abstract: A high speed integrated circuit operational amplifier chip having first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A low gain differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating.

Abstract: A high speed integrated circuit operational amplifier chip first, second, third and fourth successive edges includes a thermal centerline parallel to the second and fourth edges. An output driver circuit is located adjacent to an output bonding pad along the third edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced differential heating of the operational amplifier chip relative to the thermal centerline. A differential input circuit is located adjacent to the first edge and is disposed approximately symmetrically about the thermal centerline to provide approximately balanced responses of matched transistors in the low gain differential input circuit to isotherms produced by the differential heating. The most thermally sensitive transistors are disposed along or symmetrically about the thermal centerline to provide approximately balanced response by such transistors to differential heating by the output driver circuit.

Abstract: A compensation circuit in a high speed integrated circuit operational amplifier that includes an input stage having first and second outputs connected to emitters of first and second PNP cascode transistors. A base of an cascode transistor is coupled to a collector of the first PNP cascode transistor. A resistor circuit is connected between the collectors of the second PNP cascode transistor and the NPN cascode transistor. First and second inputs of a diamond follower output buffer are connected to the collectors of the NPN cascode transistor and second PNP cascode transistor, respectively. A compensation circuit includes first and second compensation capacitors connected to the collectors of the NPN cascode transistor and the second PNP cascode transistor, respectively, to prevent instability of an output voltage of the diamond follower buffer circuit.

Abstract: A hypodermic safety syringe, according to the present invention, includes a barrel having an open end, a cone shaped end and an interior surface. A hollow needle and carriage assembly is temporarily attached and is restrained by four catches extending from the interior tapered surface. A plunger assembly is reciprocally received into the barrel and is in air-tight engagement with the interior surface of the barrel. Thus, an interior chamber is formed in the barrel whereby liquids are retreived and emmited through the hollow needle. A cavity within the plunger contains a spring and retraction guide assembly with a mating member corresponding to mating members extending from the needle carriage. As the mating members contact and become captured the needle and carriage assembly is released by the approaching plunger assembly as the catches are deflected outward by the angled surface of the plunger.

Abstract: A hypodermic safety syringe, according to the present invention, includes a barrel having an open end, a cone shaped end and an interior surface. A hollow needle and carriage assembly is temporarily attached and is restrained by four catches extending from the interior tapered surface. A plunger assembly is reciprocally received into the barrel and is in air-tight engagement with the interior surface of the barrel. Thus, an interior chamber is formed in the barrel whereby liquids are retrieved and emitted through the hollow needle. A cavity within the plunger contains a spring and retraction guide assembly with a mating member corresponding to mating members extending from the needle carriage. As the mating members contact and become captured the needle and carriage assembly is released by the approaching plunger assembly as the catches are deflected outward by the angled surface of the plunger.

Abstract: An industrial I/O controller is implemented on a processor board and includes two I/O daughter boards which are mounted on and parallel to the processor board by means of connectors such that the entire system occupies only a single slot space of a VMEbus back plane. The processor board includes a VMEbus connector attached to its upper right-hand edge. First buffer circuitry, a static RAM, second buffer circuitry and an EPROM are located from right to left along the upper edge of the processor board. Two connectors for attachment of two I/O daughter boards are located in the lower part of the processor board.

Abstract: An analog output system coupled to a digital system bus (1, FIG. 1) comprises a RAM (8) in which digital data may be input from the system bus. The data is converted into analog form by digital-to-analog converters (30-37) in either continuous mode or intermittent mode, depending upon the contents of control/status register (18). The system also comprises interrupt logic (6), bus arbitration control logic (16), and reconstruction filters (40-47). A watchdog timer (50) zeroes all outputs which have not been accessed via the system bus (1) within a specified time period. The conversion rate can be controlled either by an internal timer (52) or by an external trigger (57). The output channel configuration and conversion frequency are fully software programmable.

Abstract: In a data processing system in which the program memory unit and the internal data memory unit are separately addressed, and which special instructions for transferring data between these two units are available, apparatus and method are described for increasing the memory available for the internal data memory unit. The increased storage space takes the form of an auxiliary data memory unit that is activated when the special instruction for the transfer of data signal groups between the program memory unit and the data memory unit are evoked. Apparatus is provided for identifying the presence of the special instructions, and this identification generates the signals for inactivating the program memory unit and for activating the auxiliary data unit for the purposes of transfer of data signal groups between the internal data unit and the auxiliary data memory unit.

Abstract: A new and distinct cultivar of Metasequoia glyptostroboides plant characterized by the globose shape, slow rate of growth, golden yellow color and stable dwarf characteristic.