Abstract: An electrostatic discharge protection circuit for an electronic device includes an output buffer including a transistor having a gate configured to receive a control signal, a source connected to a voltage supply terminal, and a drain connected to a pad; and an ESD trigger circuit configured to produce a first electronic signal in response to an electrostatic voltage between the pad or the voltage supply terminal. The first electronic signal can isolate the control signal from the gate of the transistor and to turn on the transistor to discharge the electrostatic voltage between the pad and the voltage supply terminal.

Abstract: A bandgap voltage reference circuit includes a bandgap voltage generation circuit that can produce a bandgap reference voltage in response to an activation voltage signal, a start-up circuit that can produce the activation voltage signal in response to one-shot voltage pulse and an one-shot pulse generator circuit configured to produce the one-shot voltage pulse. The start-up circuit can be automatically shut off after the one-shot voltage pulse.

Abstract: An electrostatic discharge protection circuit includes a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal (VDD) and an input pad (PAD), a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal (VSS), a first capacitor connected between VDD and a node VT that is connected to gate terminals of the second NMOS transistor and the third NMOS transistor, a second capacitor connected between the node VT and PAD, and a diode connected between VDD and the node VT.

Abstract: An electrostatic discharge protection circuit includes a high-voltage supply terminal (VDD), an input/output (IO) pad, and a first shunting transistor that can discharge electrostatic charges between the IO pad and VDD in response to a control signal. A trigger circuit can output the control signal in response to an electrostatic voltage between the IO pad and VDD. The electrostatic discharge protection circuit also includes a first group of serially connected diodes, which includes a first end connected to the IO pad and a second end configured to supply power to the trigger circuit.

Abstract: An electrostatic discharge protection circuit includes a first NMOS transistor and a second NMOS transistor cascode-connected between a high-voltage supply terminal (VDD) and an input pad (PAD), a third NMOS transistor and a fourth NMOS transistor cascode-connected between PAD and a low-voltage supply terminal (VSS), a first capacitor connected between VDD and a node VT that is connected to gate terminals of the second NMOS transistor and the third NMOS transistor, a second capacitor connected between the node VT and PAD, and a diode connected between VDD and the node VT.

Abstract: A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node.

Abstract: A voltage controlled oscillator includes a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN, a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP, a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor. A first PMOS transistor includes a base terminal connected to the output node OUTP and a drain terminal connected to the output node OUTN. A second PMOS transistor includes a base terminal connected to the output node OUTN and a drain terminal connected to the output node OUTP.

Abstract: A voltage controlled oscillator includes a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN, a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP, a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor. A first PMOS transistor includes a base terminal connected to the output node OUTP and a drain terminal connected to the output node OUTN. A second PMOS transistor includes a base terminal connected to the output node OUTN and a drain terminal connected to the output node OUTP.

Abstract: An output buffer having slew-rate control and crossbar current control includes a pull-up PMOS transistor, a pull-down NMOS transistor, a pull-up network coupled to the gate of the pull-up PMOS transistor, and a pull-down network coupled to the gate of the pull-down NMOS transistor.

Abstract: A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node.

Abstract: A bandgap voltage reference circuit includes a bandgap voltage generation circuit that can produce a bandgap reference voltage in response to an activation voltage signal, a start-up circuit that can produce the activation voltage signal in response to one-shot voltage pulse and an one-shot pulse generator circuit configured to produce the one-shot voltage pulse. The start-up circuit can be automatically shut off after the one-shot voltage pulse.

Abstract: An electrostatic discharge protection circuit includes a high-voltage supply terminal (VDD), an input/output (IO) pad, and a first shunting transistor that can discharge electrostatic charges between the IO pad and VDD in response to a control signal. A trigger circuit can output the control signal in response to an electrostatic voltage between the IO pad and VDD. The electrostatic discharge protection circuit also includes a first group of serially connected diodes, which includes a first end connected to the IO pad and a second end configured to supply power to the trigger circuit.

Abstract: A power-on reset circuit includes a first circuit arranged between a high voltage supply terminal (VDD) and a low voltage supply terminal (VSS), wherein the first circuit is configured to output a low-voltage reset signal at an output node (PORB) when VDD is powered up and to output a high voltage signal at the node PORB after the VDD reaches a predetermined voltage during power up; a second circuit configured to set the node PORB to a low voltage after VDD is powered off; and a third circuit configured to provide a supply voltage at a node DV to the second circuit. The supply voltage is lower than the voltage of VDD by approximately one diode voltage.

Abstract: An electrostatic discharge protection circuit for an electronic device includes an output buffer including a transistor having a gate configured to receive a control signal, a source connected to a voltage supply terminal, and a drain connected to a pad; and an ESD trigger circuit configured to produce a first electronic signal in response to an electrostatic voltage between the pad or the voltage supply terminal. The first electronic signal can isolate the control signal from the gate of the transistor and to turn on the transistor to discharge the electrostatic voltage between the pad and the voltage supply terminal.

Abstract: An electrostatic discharge protection circuit includes a first inverter, a first transistor having a gate connected with the output of the first inverter and a drain connected with the input of the first inverter, a second transistor having a gate connected with the output of the first inverter and a source connected with the input of the first inverter, and a shunting transistor configured to discharge electrostatic charges between a first terminal and a second terminal in response to the output of the first inverter.