Abstract: An apparatus is provided and includes a housing, a block formed to define an array of holes corresponding to an array of plugs into which connectors with spring loaded sleeves are pluggable such that the block engages with a respective sleeve of each connector, the block being supportively disposed within the housing to be movable with respect to the housing between first and second block positions at which the sleeves are extended and retracted, respectively and a cam lever supported on the housing and coupled to the block, which selectively occupies first and second lever positions at which the cam lever causes the block to assume the first and second block positions, respectively.

Abstract: An apparatus is provided and includes a housing, a block formed to define an array of holes corresponding to an array of plugs into which connectors with spring loaded sleeves are pluggable such that the block engages with a respective sleeve of each connector, the block being supportively disposed within the housing to be movable with respect to the housing between first and second block positions at which the sleeves are extended and retracted, respectively and a cam lever supported on the housing and coupled to the block, which selectively occupies first and second lever positions at which the cam lever causes the block to assume the first and second block positions, respectively.

Abstract: A module assembly holding workboard is provided and includes a base having a central portion to support a computing module, a first wing at a first side of the central portion to support a first adapter and a second wing at a second side of the central portion to support a second adapter, the first and second adapters being coupled to the computing module via first and second conductive elements and a plurality of routing channel elements fixedly disposed at the first and second wings to retain the first and second conductive elements.

Abstract: A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced store operations. The self test function then generates fetch commands to read back the unique data patterns from the two DRAM addresses. In the fetch operations, the data transmission for each operation and between both operations is contiguous (no gaps). A self test data comparison function is then used to compare these fetched data words to data patterns which are generated from the self test data generator. Bit error counters from the memory controller keeps track of any miscompares. By reading out a unique signature from these bit counters, it can be determined whether the store path data are misaligned early or late or correct and/or the fetch path data are misaligned early or late or correct. In addition, the exact number of cycles the data are early or late is known.

Abstract: A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced store operations. The self test function then generates fetch commands to read back the unique data patterns from the two DRAM addresses. In the fetch operations, the data transmission for each operation and between both operations is contiguous (no gaps). A self test data comparison function is then used to compare these fetched data words to data patterns which are generated from the self test data generator. Bit error counters from the memory controller keeps track of any miscompares. By reading out a unique signature from these bit counters, it can be determined whether the store path data are misaligned early or late or correct and/or the fetch path data are misaligned early or late or correct. In addition, the exact number of cycles the data are early or late is known.

Abstract: A memory built-in self test (MBIST) apparatus and method for testing dynamic random access memory (DRAM) arrays, the DRAM arrays in communication with a memory interface device that includes interface logic and mainline chip logic. The MBIST apparatus includes a finite state machine including a command generator and logic for incrementing data and addresses under test and a command scheduler in communication with the finite state machine. The command scheduler includes resource allocation logic for spacing commands to memory dynamically utilizing DRAM timing parameters. The MBIST apparatus also includes a test memory storing subtests of an MBIST test. Each of the subtests provides a full pass through a configured address range. The MBIST apparatus further includes a subtest pointer in communication with the test memory and the finite state machine. The finite state machine implements subtest sequencing of each of the subtests via the subtest pointer.

Abstract: A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

Abstract: A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

Abstract: In a computer RAM memory system, the memory is subjected to a self test operation during which data is written to and read out from each address location of the memory. The data read out is compared with the written data to detect errors and the number of errors at each bit position is counted. When the number of errors in a bit position-exceeds a selected threshold, the corresponding DRAM is replaced by a spare DRAM. When the self test detects two or more errors in the same double word, the DRAM corresponding to the bit position having the highest error count is replaced with a spare DRAM. The memory is periodically scrubbed and errors detected during the scrubbing operation are counted for each bit position. At the end of the scrubbing of a chip row the DRAMs corresponding to bit positions at which the error counts exceed a selected threshold are replaced with spare DRAMs. When a multiple bit error in a double word is detected during scrubbing, the corresponding double word is tagged.