Abstract: A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The input of the first memory is coupled to the first buffer input. The buffer also includes a second memory. The second memory has an input and an output. The input of the second memory is coupled to the second buffer input. The buffer also includes a first register. The first register has an input and an output. The input of the first register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the first register is coupled to the buffer output. The buffer also includes a second register configured to store a second data entry. The second register has an input and an output.

Abstract: A method and mechanism for reducing data transfer latency. A request for transfer of a block of data is received. In addition, a mask is received which indicates only particular sub-blocks of the block are required. Access to the blocks are made from an interface to a control unit which is configured to transfer data in sub-block units. Each request to the control unit includes an address corresponding to a particular sub-block. In response to receiving a transfer request corresponding to a block of data, the interface is configured to concurrently generate an address corresponding to each sub-block of the block, detect which of the sub-blocks are required as part of said transfer request, and utilize only those generated addresses which correspond to the sub-blocks which are required to generate requests to the control unit. In addition, the interface is configured to determine how many sub-blocks are required by examining the received mask.

Abstract: A buffer, having a first buffer input, a second buffer input, and a buffer output. The buffer is configured to store a plurality of data entries. The buffer includes: a first memory, the first memory having an input and an output. The input of the first memory is coupled to the first buffer input. The buffer also includes a second memory. The second memory has an input and an output. The input of the second memory is coupled to the second buffer input. The buffer also includes a first register. The first register has an input and an output. The input of the first register is coupled to the first buffer input, the second buffer input, the output of the first memory, and the output of the second memory. The output of the first register is coupled to the buffer output. The buffer also includes a second register configured to store a second data entry. The second register has an input and an output.