Abstract: A system and method are provided for fairly distributing grants for access to switch outputs, through crossbars, between switch input channels. Crossbars are granted access between specified switch inputs and switch outputs, and the least recently used input channels are associated with selected switch outputs. A history of the previous channel transaction is maintained for each switch output, and channels are nominated in a rotation through a priority channel list. The present invention bid grant algorithm permits information packets to be transferred across a switch in the time between a bid submission and a bid grant.

Abstract: A system and method are provided for fairly distributing grants for access to switch outputs, through crossbars, between switch input channels. Crossbars are granted access between specified switch inputs and switch outputs, and the least recently used input channels are associated with selected switch outputs. A history of the previous channel transaction is maintained for each switch output, and channels are nominated in a rotation through a priority channel list. The present invention bid grant algorithm permits information packets to be transferred across a switch in the time between a bid submission and a bid grant.

Abstract: A system and method are provided for fairly distributing grants for access to switch outputs, through crossbars, between switch input channels. Crossbars are granted access between specified switch inputs and switch outputs, and the least recently used input channels are associated with selected switch outputs. A history of the previous channel transaction is maintained for each switch output, and channels are nominated in a rotation through a priority channel list. The present invention bid grant algorithm permits information packets to be transferred across a switch in the time between a bid submission and a bid grant.

Abstract: A system and method are provided for tolerating data line faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of ingress port card ports, the plurality of information packets addressing a plurality of egress port card ports; selectively connecting port card ports to port card backplane data links; selectively connecting port card backplane data links and crossbars; sensing a connection fault in a backplane data link; in response to sensing the fault, reselecting connections between the port card ports and the port card backplane data links; in response to reselecting connections between the port card ports and the port card backplane data links, serially transferring packets through the port cards; serially transferring packets through the crossbars to the egress port cards; and, suspending use of the faulty connection.

Abstract: A system and method are provided for resynchronizing backplane link management credit counters in a packet communications switch fabric. The method comprises: at an input port card ingress port, accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between the input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; sending the generated credits to increment the counter, using the modified destination information; and, using the generated credit flow to resynchronize the credit counter.

Abstract: A system and method are provided for communicating control information in a switch fabric. The method comprises: on a switch card, establishing a plurality of crossbars controlled by an arbiter; initiating a control message; and, distributing the control message on a switch card token bus connecting the crossbars and arbiter elements. Distributing the control message on a switch card token bus connecting the crossbar and arbiter elements includes daisy-chain connecting the elements with a cyclical bus. In some aspects of the method, establishing a plurality of crossbars controlled by an arbiter includes identifying each element with a unique address. Then, initiating a control message includes initiating a control message with an attached address. Distributing the control message on a switch card token bus includes the substeps of: daisy-chain passing the control message between elements; and, terminating the message at an element having an address matching the address attached to the control message.

Abstract: A system and method are provided for configuring interface bandwidths in a packet communications switch fabric. The method comprises: interfacing data links with a first plurality of traffic managers (TMs); differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs; and, communicating packets information with the TMs at a first plurality of data rates corresponding to the first plurality of subchannels. More specifically, differentiating port card interface ports into a first plurality of subchannels associated with the first plurality of TMs includes: differentiating a second plurality of ingress data links into a third plurality of ingress subchannels associated with a third plurality of ingress traffic managers (iTMs); and, differentiating a fourth plurality of egress data links into a fifth plurality of egress subchannels associated with a fifth plurality of egress TMs (eTMs).

Abstract: A credit-based system and method are provided for managing backplane traffic flow in a packet communications switch fabric. The method comprises: accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between an input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; and, using modified destination information, sending the generated credits to increment the counter. In some aspects, modifying the destination information in the received packet headers includes: extracting the output port card termination from the card field; and, inserting the input port card source in the card field.

Abstract: A system and method are provided for communicating TDM communications through a packet switch fabric. The method comprises: accepting native TDM frames; converting the native TDM frames to fabric-cellified TDM frames; differentiating the cells of each frame into time slots; interleaving the frame time slots; TDM scheduling the interleaved frame time slots; and, routing the interleaved frame time slots between input port cards and output port cards on backplane data links through an intervening crossbar. TDM scheduling the interleaved frame time slots includes: an input port card ingress memory subsystem (iMS) receiving a first TDM configuration schedule including interleaved frame time slots cross-referenced to backplane transmission times; and, an output port card egress MS (eMS) receiving a second TDM configuration schedule including interleaved frame time slots cross-referenced to egress channel transmission times. Then, the routing is performed in response to the TDM schedules.

Abstract: A system and method are provided for cut-through packet routing in a packet communications switch fabric. The method comprises: accepting information packets addressed to a plurality of output port card egress ports at an input port card ingress port; routing information packets between port cards on backplane data links through an intervening crossbar; maintaining a credit counter for each port card egress destination, at the input port card; decrementing the counter in response to transmitting cells in a packet from the input port card; and, incrementing the counter in response to transmitting cells from the packet at the output port card. In some aspects of the method, accepting information includes buffering the packets in an ingress memory subsystem (iMS). Routing information includes the iMS transmitting buffered packets on a selected backplane data link. Decrementing the counter includes the iMS communicating with the iPQ in response to transmitting a cell.

Abstract: A system and method are provided for tolerating data line faults in a packet communications network. The method comprises: serially transmitting information packets from at least one traffic manager (TM); at a switch fabric, accepting information packets at a plurality of ingress ports, the information packets addressing destination port card egress ports; selectively connecting port card ingress ports to port card egress ports; serially supplying information packets from a plurality of port card egress ports; sensing a connection fault between the switch fabric and the TM; and, in response to sensing the fault, reselecting connections between the switch fabric port card ports and the TM. Some aspects comprise: an ingress memory subsystem (iMS) receiving cells on an ingress port exceeding an error threshold. Then, reselecting connections between the port card ports and the TM includes the iMS sending a message to the iTM identifying the faulty ingress connection.

Abstract: A system and method are provided for tolerating control link faults in a packet communications switch fabric. The method comprises: accepting information packets including a plurality of cells, at a plurality of port card ports, the plurality of information packets addressing a plurality of port card ports; selectively connecting port card ports to port card backplane data links; in response to backplane control link communications, selectively connecting port card backplane data links and crossbars; sensing a connection fault in a control link; and, in response to sensing the control link fault, reselecting connections between the port card ports and the port card backplane data links. In some aspects, selectively connecting port card backplane data links and crossbars includes: for a particular backplane data link, fixedly connecting each port card to a corresponding interface of an assigned crossbar; and, selectively enabling the connection to each crossbar.

Abstract: A system and method have been provided for prioritizing queued information packets having a variable number of cells. A simultaneous deficit round robin (DRR) analysis occurs in the course of several selection cycles. Each queue has an associated increment value. The packet lengths in each queue are simultaneously compared to an accumulation total in every selection cycle. If all the packets have lengths greater than their corresponding accumulation totals, each accumulation total is incremented and the selection process is repeated. If one of the information packets has a number of cells less than, or equal to its corresponding accumulation total, it is selected. In case multiple information packets are eligible, a variety of selection criteria can be used to break a tie. For example, the eligible information packet with the highest class of service (COS) can be selected. The information packet is completed transferred before another selection process is begun.

Abstract: A system and method have been provided for hierarchically arbitrating in a broadband information switching network. The method promotes the fair and efficient distribution of information packets across the switch fabric that ultimately permits the switch to maximally match information packets to switch output addresses, at faster rates and higher throughput.

Abstract: Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

Abstract: A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the instruction marking circuit. A length decoder determines whether a byte being processed is a prefix byte to an instruction. If a length-affecting prefix byte is found, the length decoder signals a subsequent length decoder to indicate that a prefix byte has been found. The subsequent length decoder uses the prefix signal to appropriately length decode the byte being processed by the subsequent length decoder. Signals are provided to continue the self-timed marking process. Prefix handling may also be used in a multiple marking unit configuration of an instruction marking circuit.

Abstract: A self-timed instruction marking circuit includes a long instruction processing system to divide long instruction processing between two columns of the instruction marking circuit. Length decoders are interconnected across columns to signal the presence and length of long instructions. Self-timed marking can continue without alteration. The number of connections required by the instruction marking circuit are reduced. The marking process can be optimized to efficiently process all instructions by setting the definition of a long instruction such that commonly executed instructions are not included.

Abstract: An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.