Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

Abstract: Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

Abstract: A clock frequency divider for odd numbered divide ratios. The divider clocks two counters in parallel from a reference clock to be divided. One counter is loaded with the divide ratio and the other counter is loaded with the divide ratio except for the least significant bit. The second counter will set a latch when its count has elapsed. The first counter will reset the latch when its count has elapsed and will reload the counters. The latch is used for the divided output, but passes through a retiming circuit. The retiming circuit delays the output edge by one reference clock edge when the least significant bit indicates an odd numbered divide ratio.

Abstract: A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.

Abstract: A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchronized with the dominant clock. When the system selects another converted clock signal for use as the dominant clock, the newly selected signal already is edge-synchronized with the dominant clock and, therefore, switchover losses can be avoided. The dominant clock can be subject of further frequency translation processes and output from the system.

Abstract: A clock frequency divider for odd numbered divide ratios. The divider clocks two counters in parallel from a reference clock to be divided. One counter is loaded with the divide ratio and the other counter is loaded with the divide ratio except for the least significant bit. The second counter will set a latch when its count has elapsed. The first counter will reset the latch when its count has elapsed and will reload the counters. The latch is used for the divided output, but passes through a retiming circuit. The retiming circuit delays the output edge by one reference clock edge when the least significant bit indicates an odd numbered divide ratio.

Abstract: A phase locked loop (PLL) based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The PLL is configured as an all digital PLL and includes a bang-bang phase frequency detector, digital loop filter, and digitally-controlled oscillator. The frequency translator is located in either the reference clock path for division or the PLL feedback loop path for multiplication. The SDM produces a predictable noise characteristic set with known stochastic properties which can be used to smooth any discontinuity in the bang-bang phase frequency detector. The predictable noise of the SDM will produce a dithering delay that eliminates any hard discontinuities. This allows for a bang-bang phase frequency detector based digital PLL.

Abstract: A multi-branch frequency translation system converts a plurality of independent input clocks to a common frequency. One of the converted clock signals is selected as a dominant clock. The remaining converted clock signals are edge-synchronized with the dominant clock. When the system selects another converted clock signal for use as the dominant clock, the newly selected signal already is edge-synchronized with the dominant clock and, therefore, switchover losses can be avoided. The dominant clock can be subject of further frequency translation processes and output from the system.

Abstract: A PLL-based frequency translator provides a divider augmented with a sigma delta modulator (SDM) in a reference path. The system may include two primary functional blocks—an input PLL with its reference path containing an integer divider coupled with a SDM (a fractional frequency divider), and an output PLL with its feedback path containing an integer divider coupled with a SDM (a fractional frequency multiplier). The combination of an integer divider and an SDM yields a fractional divider that divides by N+F/M, where N is the integer portion of the division and F/M is the fractional portion of the division, with M denoting the fractional modulus. Furthermore, since it is desirable to have programmable division factors, it is beneficial to define N, F and M as integers as this simplifies a programming interface when the frequency translator is manufactured as an integrated circuit.