Abstract: A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock select signal is asynchronous to both clock sources and can be either from a programmable bit implemented under software control or as a single signal generated from some other logic block. The technique guarantees that the switching to the desired clock based on the binary value of the clock select signal onto the clock line is glitch-free. The clock switching technique is independent of the two clock source frequencies as well as the system clock frequency.

Abstract: A clock switching technique allows selecting an input clock signal from any number of clock sources. Multiplexed input clock signals are switched on the fly onto an internal clock line coupled to an output clock line. Clock glitches are allowed on the output clock line. A clock invalid signal is asserted synchronous with the internal clock line during the time clock glitches may potentially be generated. The clock invalid signal signifies that clock switching is in progress and can be used to reset circuits which use the output clock line preventing problems in those circuits typically caused by clock glitches during the period of output clock instability. The clock switching technique is independent of clock source frequency as well as the system clock frequency.

Abstract: A clock switching technique allows selecting an input clock signal from two clock sources. The two clock sources are asynchronous to one another and a clock select signal is used to determine which of the clocks will be switched onto the clock output line. The clock select signal is asynchronous to both clock sources and can be either from a programmable bit implemented under software control or as a single signal generated from some other logic block. The technique guarantees that the switching to the desired clock based on the binary value of the clock select signal onto the clock line is glitch-free. The clock switching technique is independent of the two clock source frequencies as well as the system clock frequency.

Abstract: A programmable interrupt controller arrangement is provided including a multiple number of selectably enabled programmable interrupt controllers along with a multi-channel switch matrix. A scalable number of interrupt sources can be routed to any particular interrupt request line. In addition, from the same architecture, multiple interrupt sources are allowed to share any one of the interrupt request lines. Interrupt signals are routed via the switch matrix under software control. PC/AT compatibility is achieved by selectively disabling certain of the programmable interrupt controllers.

Abstract: A microcontroller is provided with one or more synchronous serial channels, such as HDLC channels, that are coupled to time slot assigners for communication over a time division multiplex bus. The time slot assigners each include a bit position start register and a bit position stop register that allows the time slot assigner to enable and disable the associated synchronous serial channel on the arrival of a specific bit position within the time division multiplex bus frame. Further, an end of slot adjust register provides for additional bits to be placed by the time slot assigner on to the end of a slot that is transmitted by an associated synchronous serial communication channel transmitter.