Abstract: Embodiments include an electrostatic chuck assembly having an electrostatic chuck mounted on an insulator. The electrostatic chuck and insulator may be within a chamber volume of a process chamber. In an embodiment, a ground shield surrounds the electrostatic chuck and the insulator, and a gap between the ground shield and the electrostatic chuck provides an environment at risk for electric field emission. A dielectric filler can be placed within the gap to reduce a likelihood of electric field emission. The dielectric filler can have a flexible outer surface that covers or attaches to the electrostatic chuck, or an interface between the electrostatic chuck and the insulator Other embodiments are also described and claimed.

Abstract: Embodiments include an electrostatic chuck assembly having an electrostatic chuck mounted on an insulator. The electrostatic chuck and insulator may be within a chamber volume of a process chamber. In an embodiment, a ground shield surrounds the electrostatic chuck and the insulator, and a gap between the ground shield and the electrostatic chuck provides an environment at risk for electric field emission. A dielectric filler can be placed within the gap to reduce a likelihood of electric field emission. The dielectric filler can have a flexible outer surface that covers or attaches to the electrostatic chuck, or an interface between the electrostatic chuck and the insulator Other embodiments are also described and claimed.

Abstract: Embodiments include an electrostatic chuck assembly having an electrostatic chuck mounted on an insulator. The electrostatic chuck and insulator may be within a chamber volume of a process chamber. In an embodiment, a ground shield surrounds the electrostatic chuck and the insulator, and a gap between the ground shield and the electrostatic chuck provides an environment at risk for electric field emission. A dielectric filler can be placed within the gap to reduce a likelihood of electric field emission. The dielectric filler can have a flexible outer surface that covers or attaches to the electrostatic chuck, or an interface between the electrostatic chuck and the insulator Other embodiments are also described and claimed.

Abstract: Embodiments include an electrostatic chuck assembly having an electrostatic chuck mounted on an insulator. The electrostatic chuck and insulator may be within a chamber volume of a process chamber. In an embodiment, a ground shield surrounds the electrostatic chuck and the insulator, and a gap between the ground shield and the electrostatic chuck provides an environment at risk for electric field emission. A dielectric filler can be placed within the gap to reduce a likelihood of electric field emission. The dielectric filler can have a flexible outer surface that covers or attaches to the electrostatic chuck, or an interface between the electrostatic chuck and the insulator Other embodiments are also described and claimed.

Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.

Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.

Abstract: A plasma reactor for processing a workpiece such as a semiconductor wafer has a housing defining a process chamber, a workpiece support configured to support a workpiece within the chamber during processing and comprising a plasma bias power electrode. The reactor further includes plural gas sources containing different gas species, plural process gas inlets and an array of valves capable of coupling any of said plural gas sources to any of said plural process gas inlets. The reactor also includes a controller governing said array of valves and is programmed to change the flow rates of gases through said inlets over time. A ceiling plasma source power electrode of the reactor has plural gas injection zones coupled to the respective process gas inlets. In a preferred embodiment, the plural gas sources comprise supplies containing, respectively, fluorocarbon or fluorohydrocarbon species with respectively different ratios of carbon and fluorine chemistries.

Abstract: High aspect ratio contact openings are etched while preventing bowing or bending of the etch profile by forming a highly conductive thin film on the side wall of each contact opening. The conductivity of the thin film on the side wall is enhanced by ion bombardment carried out periodically during the etch process.

Abstract: A plasma etch process for etching high aspect ratio openings in a dielectric film on a workpiece is carried out in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a first polymerizing etch process gas through a radially inward one of plural concentric gas injection zones in the ceiling electrode and injecting a second polymerizing etch process gas through a radially outward one of the plural concentric gas injection zones in the ceiling electrode, the compositions of the first and second process gases having first and second carbon-to-fluorine ratios that differ from one another.

Abstract: A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an annular zone of gas injection orifices in the ceiling electrode, and evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece. The high aspect ratio openings are etched in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor by applying VHF source power and/or HF and/or LF bias power to the electrodes at the ceiling and/or the electrostatic chuck.

Abstract: High aspect ratio contact openings are etched while preventing bowing or bending of the etch profile by forming a highly conductive thin film on the side wall of each contact opening. The conductivity of the thin film on the side wall is enhanced by ion bombardment carried out periodically during the etch process.

Abstract: A plasma etch process includes injecting process gases with different compositions of chemical species through different radial gas injection zones of an overhead electrode to establish a desired distribution of chemical species among the plural gas injection zones.

Abstract: Apparatus for plasma etching a layer of material upon a substrate comprising an anode having a first region protruding from a second region, wherein the second region defines a plane and the first region extends from said plane. In one embodiment, at least one solenoid is disposed near the apparatus to magnetize the plasma.

Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.

Abstract: Apparatus for plasma etching a layer of material upon a substrate comprising an anode having a first region protruding from a second region, wherein the second region defines a plane and the first region extends from said plane. In one embodiment, at least one solenoid is disposed near the apparatus to magnetize the plasma.

Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.

Abstract: A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer.

Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.

Abstract: A plasma reactor for processing a semiconductor workpiece, includes a vacuum chamber including a side wall and an overhead ceiling, a wafer support pedestal within the vacuum chamber, gas injection passages to the interior of the vacuum chamber coupled to a process gas supply, and a first RF power source for applying RF power to the wafer support pedestal for generating a capacitively coupled plasma. It further includes plural electromagnets near said chamber, and a time-varying current source connected to said plural electromagnets for producing a magnet field that rotates relative to said wafer pedestal. An inductive plasma source power applicator is provided near said chamber and a second RF power source is provided for applying RF power to said inductive plasma source power applicator for generating an inductively coupled plasma within said chamber.

Abstract: A method for etching a dielectric in a thermally controlled plasma etch chamber with an expanded processing window. The method is adapted to incorporate benefits of a the thermal control and high evacuation capability of the chamber. Etchent gases include hydrocarbons, oxygen and inert gas. Explanation is provided for enablling the use of hexafluoro-1,3-butadiene in a capacitively coupled etch plasma. The method is very useful for creating via, self aligned contacts, dual damascene, and other dielectric etch.