Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations, An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations, An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of tracks, wherein each track comprises a plurality of data sectors comprising a disk block size. A host write command is received comprising data blocks having a host block size less than the disk block size. A misalignment is detected between the data blocks and the disk block size, and when the misalignment is detected, at least one of the data blocks is stored in a write cache. A command rate limit is adjusted as a function of the write cache, wherein the command rate limit defines a limit on a number of commands received from a host.

Abstract: A data storage device is disclosed comprising a non-volatile memory. A command rate profile is initialized, wherein the command rate profile defines a limit on a number of access commands received from a host as a function of an internal parameter of the data storage device. The command rate profile is adjusted in response to a change in operating mode.

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

Abstract: An apparatus for performing secure operations with a dedicated secure processor is described in one embodiment. The apparatus includes security firmware defining secure operations, a processor configured to execute the security firmware and perform a set of operations limited to the secure operations, and a plurality of secure hardware registers, accessible by the processor and configured to receive instructions to perform the secure operations. An apparatus for performing secure operations with a plurality of security assist hardware circuits is described in another embodiment. The apparatus comprises one or more secure hardware registers configured to receive a command to perform secure operations and one or more security assist hardware circuits configured to perform discrete secure operations using one or more secret data objects.

Abstract: A disk drive is disclosed comprising a disk, a head, and a ramp located near an outer periphery of the disk. The disk drive further comprises control circuitry operable to load the head off the ramp over the disk, receive an unload command to perform an unload operation, evaluate a number of unloads relative to an unload limit that varies over time, and when the number of unloads exceeds the unload limit, delay the unload operation.

Abstract: Systems and methods for writing a sequence of data to a disk drive using sorted data zones are provided. One embodiment includes a disk drive comprising one or more disks having a plurality of disk surfaces, wherein each disk surface comprises a plurality of data zones, each data zone having a data transfer rate; a plurality of heads, wherein each head is configured to write data to a respective one of the disk surfaces; and a controller configured to operate the plurality of heads to sequentially write a sequence of data blocks to the plurality of disk surfaces in accordance with an order of head-zone combinations ordered from highest data transfer rate to lowest data transfer rate, each head-zone combination corresponding to one of the heads and one of the data zones of the respective disk surface.

Abstract: A data storage device is disclosed comprising a non-volatile memory and control circuitry operable to evaluate a physical feature of the data storage device, wherein the physical feature is physically alterable by a user. When the physical feature is in a first state, host access to first secure data stored in the non-volatile memory is enabled, and when the physical feature is in a second state, the host access to the first secure data is disabled and host access to second data stored in the non-volatile memory is enabled.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors. The hybrid drive further comprises a non-volatile semiconductor memory (NVSM) comprising a plurality of memory segments. A disk cache is defined comprising a first plurality of the data sectors, and a non-cache area of the disk is defined comprising a second plurality of the data sectors. When a write command is received from a host, data is written to the disk cache, and under certain conditions, the data is copied from the disk cache to the NVSM.

Abstract: A disk drive is disclosed comprising a first disk surface comprising a plurality of tracks, wherein each track comprises a number of data sectors and a number of servo sectors, and a second disk surface comprising a plurality of tracks, wherein each track comprises a number of data sectors and a number of servo sectors. A first repeatable runout (RRO) sinusoid is generated representing an RRO of the first disk surface, and a second RRO sinusoid is generated representing an RRO of the second disk surface. A plurality of access commands are received from a host which are stored in a command queue, and one of the access commands is selected to execute in response to the first and second RRO sinusoids.

Abstract: Systems and methods for writing a sequence of data to a disk drive using sorted data zones are provided. In one embodiment, a multi-head disk drive comprises a plurality of disk surfaces, wherein each disk surface comprises a plurality of data zones, each data zone having a data transfer rate different from the other zones of the respective disk surface. The multi-head disk drive also comprises a head assembly comprising a plurality of heads, wherein each head is configured to write data to a respective one of the disk surfaces, and a controller configured to operate the plurality of heads to sequentially write a sequence of data blocks to the plurality of disk surfaces in accordance with a list of head-zone combinations ordered from highest data rate to lowest data rate, each head-zone combination corresponding to one of the heads and a data zone of the respective disk surface.

Abstract: A data storage device is disclosed comprising a non-volatile memory, such as a disk of a disk drive or a non-volatile semiconductor memory. First and second write commands are received from a host, and in response first and second write data are requested from the host. The first write data is stored in the non-volatile memory, and after storing the first write data, a first acknowledge is transmitted to the host to acknowledge completion of the first write command. After transmitting the first acknowledge, a third write command is received from the host. The second write data is stored in the non-volatile memory, and after storing the second write data, a second acknowledge is transmitted to the host acknowledging completion of the second write command. After transmitting the second acknowledge, third write data is requested from the host associated with the third write command.

Abstract: A disk drive is disclosed comprising a head actuated over a disk comprising a plurality of physical zones including a first physical zone and a second physical zone, wherein the first physical zone comprises data tracks recorded at a first data rate and the second physical zone comprises data tracks recorded at a second data rate different than the first data rate. A write command is received including data and at least one logical block address (LBA). One of the first and second physical zones is selected based on a power parameter affecting a power consumption of the disk drive, and the data is written to a data sector in the selected physical zone. A physical block address (PBA) is assigned to the data sector, and an LBA to PBA map is updated for the written data.

Abstract: A disk drive is disclosed wherein a plurality of access commands received from a host are stored in a command queue. An access cost for at least a first and second access command in the command queue is generated, wherein each access cost comprises a seek length and a rotation latency. A first access command is selected from the command queue having a first access cost, and a window is defined relative to the first access cost and a first risk based penalty (RBP) of the first access command, wherein the first RBP represents a probability of missing a first data sector of the first access command. A second access command is selected from the command queue comprising a second access cost within the window. A choice is made between the first and second access commands in response to a second RBP of the second access command.

Abstract: A disk drive is disclosed comprising a first disk surface comprising a plurality of tracks, wherein each track comprises a number of data sectors and a number of servo sectors, and a second disk surface comprising a plurality of tracks, wherein each track comprises a number of data sectors and a number of servo sectors. A first repeatable runout (RRO) sinusoid is generated representing an RRO of the first disk surface, and a second RRO sinusoid is generated representing an RRO of the second disk surface. A plurality of access commands are received from a host which are stored in a command queue, and one of the access commands is selected to execute in response to the first and second RRO sinusoids.

Abstract: Servo-related tasks are performed at a first processor in a disk drive. A signal indicative of an environmental condition is received at the first processor, and code associated with the environmental condition is identified based at least in part on the signal. A second processor in the disk drive is caused to execute the code associated with the environmental condition, and a responsive task is performed at the first processor based at least in part on the executed code associated with the environmental condition.

Abstract: A host activity measure indicative of a frequency of disk access commands received by a disk drive is determined, and then compared against a host activity threshold. A subsystem activity measure indicative of an activity level of a disk drive subsystem is also determined, and then compared against a subsystem activity threshold. Based at least in part on a determination that 1) the host activity measure is indicative of a greater frequency of disk access commands than the host activity threshold, and 2) the subsystem activity measure is indicative of less activity than the subsystem activity threshold, an operating frequency of a disk drive processor is increased.