Patents by Inventor Kenpei Nakamura

Kenpei Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220399253
    Abstract: Provided is a semiconductor device including: a lead frame having an upper surface provided with a concave portion and a lower surface provided with a convex portion; a semiconductor chip fixed to the upper surface of the lead frame; a solder layer provided in the concave portion and fixing the semiconductor chip to the upper surface of the lead frame; and a sealing resin for sealing the semiconductor chip and the lead frame. A thickness of the solder layer is larger than a depth of the concave portion. The sealing resin covers at least a part of the lower surface of the lead frame. At least a part of the convex portion of the lead frame is exposed from the sealing resin.
    Type: Application
    Filed: April 25, 2022
    Publication date: December 15, 2022
    Inventor: Kenpei NAKAMURA
  • Patent number: 11244889
    Abstract: A semiconductor device includes a semiconductor element, a bonding wire that is electrically connected to the semiconductor element, a connection terminal, and sealing material that seals the semiconductor element, the bonding wire, and a part of the connection terminal. In addition, the connection terminal includes a plate-shaped lead part having a bonding area to which the bonding wire is bonded and an anchor part protruding from a first side part of the lead part. In the semiconductor device, since the rear surface of a die pad and the rear surface of the lead part exposed to the outside in a sealing main surface of the sealing material occupy a predetermined area or more, the heat dissipation of the semiconductor device is improved.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: February 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihiro Yasuda, Kenpei Nakamura
  • Patent number: 11177196
    Abstract: A lead frame is provided with a die pad portion, a first lead portion, a second lead portion, and an extension portion extending from a corner portion neighborhood of the die pad portion to the outside of the die pad portion. The first lead portion has a first terminal portion and a first lead post portion positioned on a side closer to the die pad portion relative to the first terminal portion and electrically connected to the first terminal portion. The second lead portion has a second terminal portion, a third terminal portion positioned between the first terminal portion and the second terminal portion, and a second lead post portion positioned on a side closer to the die pad portion relative to the second terminal portion and the third terminal portion and electrically connected to the second terminal portion and the third terminal portion.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keisuke Tabira, Kenpei Nakamura, Mitsuaki Matsuse, Hiroaki Furihata
  • Patent number: 10916490
    Abstract: Provided is a semiconductor device including a semiconductor chip; a frame member having a chip placement surface on which the semiconductor chip is provided; and a first suspension lead and a second suspension lead connected to the frame member and provided on any side of the frame member, wherein M1?L1+L2 is satisfied, where L1 is a distance from an arrangement position of the first suspension lead to a corner of the chip placement surface close to the first suspension lead, L2 is a distance from an arrangement position of the second suspension lead to a corner of the chip placement surface close to the second suspension lead, and M1 is a distance from the arrangement position of the first suspension lead to the arrangement position of the second suspension lead.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 9, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihiro Yasuda, Takayuki Shimatou, Kenpei Nakamura
  • Publication number: 20200312754
    Abstract: A semiconductor device includes a semiconductor element, a bonding wire that is electrically connected to the semiconductor element, a connection terminal, and sealing material that seals the semiconductor element, the bonding wire, and a part of the connection terminal. In addition, the connection terminal includes a plate-shaped lead part having a bonding area to which the bonding wire is bonded and an anchor part protruding from a first side part of the lead part. In the semiconductor device, since the rear surface of a die pad and the rear surface of the lead part exposed to the outside in a sealing main surface of the sealing material occupy a predetermined area or more, the heat dissipation of the semiconductor device is improved.
    Type: Application
    Filed: February 24, 2020
    Publication date: October 1, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshihiro YASUDA, Kenpei NAKAMURA
  • Publication number: 20200161227
    Abstract: A lead frame is provided with a die pad portion, a first lead portion, a second lead portion, and an extension portion extending from a corner portion neighborhood of the die pad portion to the outside of the die pad portion. The first lead portion has a first terminal portion and a first lead post portion positioned on a side closer to the die pad portion relative to the first terminal portion and electrically connected to the first terminal portion. The second lead portion has a second terminal portion, a third terminal portion positioned between the first terminal portion and the second terminal portion, and a second lead post portion positioned on a side closer to the die pad portion relative to the second terminal portion and the third terminal portion and electrically connected to the second terminal portion and the third terminal portion.
    Type: Application
    Filed: September 25, 2019
    Publication date: May 21, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Keisuke TABIRA, Kenpei Nakamura, Mitsuaki Matsuse, Hiroaki Furihata
  • Publication number: 20190252302
    Abstract: Provided is a semiconductor device including a semiconductor chip; a frame member having a chip placement surface on which the semiconductor chip is provided; and a first suspension lead and a second suspension lead connected to the frame member and provided on any side of the frame member, wherein M1?L1+L2 is satisfied, where L1 is a distance from an arrangement position of the first suspension lead to a corner of the chip placement surface close to the first suspension lead, L2 is a distance from an arrangement position of the second suspension lead to a corner of the chip placement surface close to the second suspension lead, and M1 is a distance from the arrangement position of the first suspension lead to the arrangement position of the second suspension lead.
    Type: Application
    Filed: December 21, 2018
    Publication date: August 15, 2019
    Inventors: Yoshihiro YASUDA, Takayuki SHIMATOU, Kenpei NAKAMURA