Patents by Inventor Kenro Kubota
Kenro Kubota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097658Abstract: A semiconductor device includes a first pad, a second pad, a first output driver provided for the first pad and configured to output a first transmission signal to the first pad, a second output driver provided for the second pad and configured to output a second transmission signal to the second pad, a register that stores first and second calibration values, a first reference resistor for the first pad and having a resistance value that is set according to the first calibration value, a second reference resistor for the second pad and having a resistance value that is set according to the second calibration value, a first setting circuit configured to calibrate a resistance value of the first output driver using the first reference resistor, and a second setting circuit configured to calibrate a resistance value of the second output driver using the second reference resistor.Type: ApplicationFiled: March 3, 2023Publication date: March 21, 2024Inventors: Fumiya WATANABE, Toshifumi WATANABE, Kazuhiko SATOU, Shouichi OZAKI, Kenro KUBOTA, Atsuko SAEKI, Ryota TSUCHIYA, Harumi ABE
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Publication number: 20240079067Abstract: A semiconductor memory device includes an output pin configured for connection with a memory controller, an output circuit configured to output through the output pin a voltage signal that changes over time in accordance with one or more bits of data to be output to the memory controller, and a control circuit configured to temporarily change a drive capability of the output circuit each time a voltage signal corresponding to one bit of the data is output through the output pin.Type: ApplicationFiled: February 28, 2023Publication date: March 7, 2024Inventors: Shouichi OZAKI, Kazuhiko SATOU, Kenro KUBOTA, Fumiya WATANABE, Atsuko SAEKI, Ryota TSUCHIYA, Harumi ABE, Toshifumi WATANABE
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Publication number: 20230223938Abstract: A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.Type: ApplicationFiled: March 22, 2023Publication date: July 13, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Patent number: 11637555Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: GrantFiled: January 31, 2022Date of Patent: April 25, 2023Assignee: Kioxia CorporationInventors: Junya Matsuno, Kensuke Yamamoto, Ryo Fukuda, Masaru Koyanagi, Kenro Kubota, Masato Dome
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Patent number: 11568935Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: GrantFiled: May 25, 2021Date of Patent: January 31, 2023Assignee: Kioxia CorporationInventors: Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi, Kensuke Yamamoto, Masato Dome, Kei Shiraishi, Junya Matsuno, Kenro Kubota
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Publication number: 20230028971Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: ApplicationFiled: October 3, 2022Publication date: January 26, 2023Applicant: Kioxia CorporationInventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
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Publication number: 20230018613Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.Type: ApplicationFiled: September 26, 2022Publication date: January 19, 2023Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Patent number: 11495308Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventors: Junya Matsuno, Kenro Kubota, Masato Dome, Kensuke Yamamoto, Kei Shiraishi, Kazuhiko Satou, Ryo Fukuda, Masaru Koyanagi
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Patent number: 11495307Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: GrantFiled: March 16, 2021Date of Patent: November 8, 2022Assignee: KIOXIA CORPORATIONInventors: Masato Dome, Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota
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Publication number: 20220158639Abstract: A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Publication number: 20220093188Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kenro KUBOTA, Masato DOME, Kensuke YAMAMOTO, Kei SHIRAISHI, Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI
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Publication number: 20220093185Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.Type: ApplicationFiled: March 16, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Masato DOME, Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA
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Patent number: 11277134Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: GrantFiled: August 26, 2020Date of Patent: March 15, 2022Assignee: KlOXIA CORPORATIONInventors: Junya Matsuno, Kensuke Yamamoto, Ryo Fukuda, Masaru Koyanagi, Kenro Kubota, Masato Dome
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Publication number: 20220059165Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.Type: ApplicationFiled: May 25, 2021Publication date: February 24, 2022Applicant: Kioxia CorporationInventors: Kazuhiko SATOU, Ryo FUKUDA, Masaru KOYANAGI, Kensuke YAMAMOTO, Masato DOME, Kei SHIRAISHI, Junya MATSUNO, Kenro KUBOTA
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Patent number: 11232051Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.Type: GrantFiled: August 21, 2020Date of Patent: January 25, 2022Assignee: Kioxia CorporationInventors: Kensuke Yamamoto, Masaru Koyanagi, Ryo Fukuda, Junya Matsuno, Kenro Kubota, Masato Dome
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Publication number: 20210271615Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.Type: ApplicationFiled: August 21, 2020Publication date: September 2, 2021Applicant: Kioxia CorporationInventors: Kensuke YAMAMOTO, Masaru KOYANAGI, Ryo FUKUDA, Junya MATSUNO, Kenro KUBOTA, Masato DOME
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Publication number: 20210226632Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.Type: ApplicationFiled: August 26, 2020Publication date: July 22, 2021Applicant: Kioxia CorporationInventors: Junya MATSUNO, Kensuke YAMAMOTO, Ryo FUKUDA, Masaru KOYANAGI, Kenro KUBOTA, Masato DOME
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Patent number: 10586599Abstract: A semiconductor storage device in an embodiment includes a memory cell array, a pad to which data is inputted, an ODT circuit connected to the pad, an ODT driver configured to drive the ODT circuit, and a control circuit configured to supply an enable signal and a resistance value control signal to the ODT driver. The pad is arranged between the memory cell array and a first end side of the semiconductor storage device, and the ODT circuit is arranged between the pad and the first end side. The ODT driver is arranged between the ODT circuit and the first end side. An ODT control signal line configured to transmit a resistance value control signal, and an ODT enable signal line configured to transmit an enable signal are arranged between the ODT driver and the first end side.Type: GrantFiled: September 10, 2019Date of Patent: March 10, 2020Assignee: Toshiba Memory CorporationInventors: Kenro Kubota, Shouichi Ozaki, Yasuhiro Suematsu
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Patent number: 10360982Abstract: The present embodiment discloses a semiconductor memory device which includes a memory cell array, a signal pad, a first voltage pad, a first regulation circuit and a first operation circuit. The signal pad supplies an output signal associated with the memory cell array. The first voltage pad receives a first voltage. The first regulation circuit regulates a signal output from the signal pad. The first operation circuit operates the first regulation circuit. The first regulation circuit and the first operation circuit are provided between the signal pad and the first voltage pad.Type: GrantFiled: September 12, 2017Date of Patent: July 23, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Suematsu, Masaru Koyanagi, Satoshi Inoue, Kenro Kubota
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Publication number: 20180277219Abstract: The present embodiment discloses a semiconductor memory device which includes a memory cell array, a signal pad, a first voltage pad, a first regulation circuit and a first operation circuit. The signal pad supplies an output signal associated with the memory cell array. The first voltage pad receives a first voltage. The first regulation circuit regulates a signal output from the signal pad. The first operation circuit operates the first regulation circuit. The first regulation circuit and the first operation circuit are provided between the signal pad and the first voltage pad.Type: ApplicationFiled: September 12, 2017Publication date: September 27, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro SUEMATSU, Masaru KOYANAGI, Satoshi INOUE, Kenro KUBOTA