Patents by Inventor Kenro Nakamura
Kenro Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9865502Abstract: The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.Type: GrantFiled: March 7, 2016Date of Patent: January 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kenro Nakamura
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Patent number: 9842773Abstract: The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.Type: GrantFiled: March 7, 2016Date of Patent: December 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Kenro Nakamura
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Patent number: 9673147Abstract: A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.Type: GrantFiled: January 25, 2016Date of Patent: June 6, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kenro Nakamura, Hirokazu Ezawa
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Publication number: 20160268163Abstract: The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.Type: ApplicationFiled: March 7, 2016Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kenro NAKAMURA
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Publication number: 20160141247Abstract: A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.Type: ApplicationFiled: January 25, 2016Publication date: May 19, 2016Inventors: Kenro NAKAMURA, Hirokazu EZAWA
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Patent number: 9287225Abstract: A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.Type: GrantFiled: February 26, 2014Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kenro Nakamura, Hirokazu Ezawa
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Publication number: 20160064265Abstract: According to one embodiment, there is provided a temporarily bonding support substrate including an underlayer and a heat generable layer. A device substrate is to be temporarily bonded to the heat generable layer on an opposite side of the underlayer.Type: ApplicationFiled: February 27, 2015Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Kenro NAKAMURA
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Patent number: 9123717Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.Type: GrantFiled: July 30, 2013Date of Patent: September 1, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kenro Nakamura, Mitsuyoshi Endo, Kazuyuki Higashi, Takashi Shirono
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Publication number: 20150028493Abstract: A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.Type: ApplicationFiled: February 26, 2014Publication date: January 29, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenro NAKAMURA, Hirokazu EZAWA
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Publication number: 20140242779Abstract: According to one embodiment, a semiconductor device manufacturing method includes: bonding a first wafer and a second wafer to each other, to form a stack; rubbing a film attached with a fill material in a thin-film shape into a gap located between a bevel of the first wafer and a bevel of the second wafer, to fill the gap with the fill material; and thinning the first wafer.Type: ApplicationFiled: July 30, 2013Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kenro NAKAMURA, Mitsuyoshi ENDO, Kazuyuki HIGASHI, Takashi SHIRONO
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Publication number: 20110081832Abstract: In one embodiment, a polishing device includes: a rotatable turntable, a holding unit, a separation wall, a slurry supply tube, and a cooling medium supply tube. On an upper surface of the rotatable turntable, a polishing pad is attached. The holding unit rotatably holds an object to be polished and disposes a polished surface of the object to be polished in a manner to face the polishing pad. The separation wall abuts on the upper surface of the polishing pad and sections the polishing pad into a polished region in which the holding unit is provided and an unpolished region in which the holding unit is not provided. The slurry supply tube supplies a slurry to the upper surface of the polishing pad in a polished region side. The cooling medium supply tube supplies a cooling medium to the upper surface of the polishing pad in the unpolished region.Type: ApplicationFiled: June 4, 2010Publication date: April 7, 2011Inventors: Kenro Nakamura, Yukiteru Matsui, Takeshi Nishioka
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Publication number: 20080188167Abstract: A substrate processing apparatus has a polishing tape and a polishing head for pressing the polishing tape against a peripheral portion of a semiconductor wafer. The substrate processing apparatus polishes the wafer due to sliding contact of the polishing tape and the wafer. The polishing head has an elastic body for supporting the polishing tape. The substrate processing apparatus has an air cylinder for pressing the polishing head so that the elastic body of the polishing head presses the polishing tape against the predetermined portion of the wafer under a constant force.Type: ApplicationFiled: April 1, 2008Publication date: August 7, 2008Inventors: You Ishii, Masayuki Nakanishi, Kenro Nakamura
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Patent number: 7367873Abstract: A substrate processing apparatus has a polishing tape and a polishing head for pressing the polishing tape against a peripheral portion of a semiconductor wafer. The substrate processing apparatus polishes the wafer due to sliding contact of the polishing tape and the wafer. The polishing head has an elastic body for supporting the polishing tape. The substrate processing apparatus has an air cylinder for pressing the polishing head so that the elastic body of the polishing head presses the polishing tape against the predetermined portion of the wafer under a constant force.Type: GrantFiled: February 12, 2003Date of Patent: May 6, 2008Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: You Ishii, Masayuki Nakanishi, Kenro Nakamura
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Patent number: 7354861Abstract: Disclosed is a method for polishing a surface of a substrate containing Ru or a Ru compound in a surface region, said method comprising a polishing step with a polishing liquid containing tetravalent cerium ions. The polishing liquid is prepared by adding a compound having a tetravalent cerium ion or its solution to a solvent in or immediately before the polishing step of the substrate.Type: GrantFiled: December 2, 1999Date of Patent: April 8, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Kenro Nakamura, Takeo Kubota, Gaku Minamihaba
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Patent number: 7351131Abstract: In manufacturing a semiconductor device, a part of an element is formed on the surface of a substrate, and at least a periphery of the substrate is polished using a polishing member stretched around the periphery of the substrate so that a polishing face of the polishing member is slid on a polishing target surface of the periphery.Type: GrantFiled: July 12, 2005Date of Patent: April 1, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Kenro Nakamura, Naoto Miyashita, Takashi Yoda, Katsuya Okumura
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Patent number: 7066787Abstract: A substrate processing apparatus is used for removing surface irregularities occurring on a peripheral portion (a bevel portion, an edge portion, and a notch) of a substrate, such as a semiconductor wafer, and films deposited as a contaminant on the peripheral portion of such a substrate. The substrate processing apparatus includes an edge-portion polisher for pressing a polishing tape against an edge portion of a substrate and causing relative movement between the polishing tape and the substrate to polish the edge portion of the substrate, and a bevel-portion polisher for pressing a polishing tape against a bevel portion of the substrate and causing relative movement between this polishing tape and the substrate to polish the bevel portion of the substrate.Type: GrantFiled: January 28, 2004Date of Patent: June 27, 2006Assignees: Ebara Corporation, Kabushiki Kaisha ToshibaInventors: Masayuki Nakanishi, You Ishii, Kenro Nakamura
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Publication number: 20050254998Abstract: A reactive detection chip having spots formed by immobilizing a plurality of porous particles in a cluster onto a substrate, the porous particles having probe molecules bound to surfaces of the porous particles and surfaces of pores in the particles including pores, wherein the porous particles are transparent to incident light, and have been immobilized in a single-layered state onto the substrate, is provided. A spotter suitable for spotting a liquid containing low dispersibility particles in manufacturing the reactive detection chip is also provided. In the reactive detection chip, the number of probes can be stably controlled, and a three-dimensional array of the probes uniformizes the supply of a sample to the probes. Thus, the magnitude of signal components is stabilized, and signal components are stably increased, so that the S/N ratio is increased, and the detection capability of the DNA chip can be enhanced. The use of the spotter enables the chip to be manufactured more efficiently.Type: ApplicationFiled: February 28, 2005Publication date: November 17, 2005Applicant: Ebara CorporationInventors: Kenro Nakamura, Masahito Abe, Naoaki Ogure
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Publication number: 20050250423Abstract: In manufacturing a semiconductor device, a part of an element is formed on the surface of a substrate, and at least a periphery of the substrate is polished using a polishing member stretched around the periphery of the substrate so that a polishing face of the polishing member is slid on a polishing target surface of the periphery.Type: ApplicationFiled: July 12, 2005Publication date: November 10, 2005Inventors: Kenro Nakamura, Naoto Miyashita, Takashi Yoda, Katsuya Okumura
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Patent number: 6933234Abstract: In manufacturing a semiconductor device, a part of an element is formed on the surface of a substrate, and at least a periphery of the substrate is polished using a polishing member stretched around the periphery of the substrate so that a polishing face of the polishing member is slid on a polishing target surface of the periphery.Type: GrantFiled: November 25, 2002Date of Patent: August 23, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Kenro Nakamura, Naoto Miyashita, Takashi Yoda, Katsuya Okumura
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Publication number: 20040185751Abstract: A substrate processing apparatus is used for removing surface irregularities occurring on the peripheral portion (a bevel portion, an edge portion, and a notch) of a substrate such as a semiconductor wafer and films deposited as a contaminant on the peripheral portion of such a substrate. The substrate processing apparatus includes an edge-portion polisher for pressing a polishing tape against an edge portion of a substrate and making a relative movement between the polishing tape and the substrate to polish the edge portion of the substrate, and a bevel-portion polisher for pressing a polishing tape against a bevel portion of the substrate and making a relative movement between the polishing tape and the substrate to polish the bevel portion of the substrate.Type: ApplicationFiled: January 28, 2004Publication date: September 23, 2004Inventors: Masayuki Nakanishi, You Ishii, Kenro Nakamura