Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

Abstract: A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory sub-block and a second memory sub-block arranged in a first direction and a control circuit. The first memory sub-block includes a first memory cell and a first word line connected to the first memory cell. The second memory sub-block includes a second memory cell and a second word line connected to the second memory cell. The control circuit executes a first and a second write operation on the first memory cell. In the first write operation, the control circuit applies a program voltage to the first word line and a first unselect write voltage to the second word line. In the second write operation, the program voltage is applied to the first word line and a second unselect write voltage is applied to the second word line.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

Abstract: According to this embodiment, a semiconductor device includes a semiconductor substrate, element formation regions that are formed in a line-and-space pattern in a surface layer portion of the semiconductor substrate to extend in a first direction, a coupling portion that is formed in the surface layer portion of the semiconductor substrate to couple the element formation regions adjacent to each other in a second direction intersecting the first direction, a source line that is disposed in an upper layer of the semiconductor substrate through an insulating film, a source line contact, having a circular shape or an elliptical shape, that is provided to electrically connect a source region pattern and the source lines by passing through the insulating film, when a region including the coupling portion and portions of the element formation regions coupled by the coupling portion is set to the source region pattern, and a bit line contact, having a circular shape or an elliptical shape, that is provided to elect

Abstract: According to this embodiment, a semiconductor device includes a semiconductor substrate, element formation regions that are formed in a line-and-space pattern in a surface layer portion of the semiconductor substrate to extend in a first direction, a coupling portion that is formed in the surface layer portion of the semiconductor substrate to couple the element formation regions adjacent to each other in a second direction intersecting the first direction, a source line that is disposed in an upper layer of the semiconductor substrate through an insulating film, a source line contact, having a circular shape or an elliptical shape, that is provided to electrically connect a source region pattern and the source lines by passing through the insulating film, when a region including the coupling portion and portions of the element formation regions coupled by the coupling portion is set to the source region pattern, and a bit line contact, having a circular shape or an elliptical shape, that is provided to elect

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a memory area, a capacitor area, and a transistor area, on a semiconductor substrate. The nonvolatile semiconductor memory device comprises a memory cell and a select gate transistor, in the memory area. The nonvolatile semiconductor memory device includes a capacitor comprising a first electrode layer and a second electrode layer stacked on the first electrode layer via an insulating layer. An upper surface of the capacitor is covered by a first insulating layer, and the insulating layer has an upper level portion and a lower level portion. A part of an outline of the upper level portion is along a part of an outline of the second electrode layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a memory cell provided on the semiconductor substrate. The memory cell includes a first insulating film provided on the semiconductor substrate, a first conductive layer provided on the first insulating film, a first insulating layer provided on the first conductive layer, and a first silicide layer including a silicide provided on the first insulating layer to contact the first insulating layer.