Abstract: To provide a curable composition for forming a low refractive index film of which a cured film excellent in heat resistance can be formed. A curable composition for forming a low refractive index film containing a hollow filler (A), a polymerizable compound (B), and a polymerization initiator (C), and not containing an alkali-soluble resin. The polymerizable compound (B) includes a compound (B1) having 5 or more polymerizable functional groups and a compound (B2) having 1 or more and 3 or less polymerizable functional groups. A ratio (B1/B2) of a mass of the compound (B1) to a mass of the compound (B2) is 0.25 or more and 3 or less.

Abstract: A photocurable composition including metal oxide nanoparticles (X) and a photopolymerizable sulfur compound (C).

Abstract: A photocurable composition containing metal oxide nanoparticles (X), a photopolymerizable compound (B), and a photoradical polymerization initiator (C), in which the content of the photoradical polymerization initiator (C) is 10 parts by mass or more with respect to 100 parts by mass of the total content of the metal oxide nanoparticles (X) and the photopolymerizable compound (B).

Abstract: According to one embodiment, a semiconductor memory device includes memory cells and a control circuit configured to control an erase operation on the memory cells. The control circuit sequentially executes, in the erase operation, a first erase process, a first erase verify process, a second erase process, and a second erase verify process on the memory cells, acquires, in the first erase verify process, first memory cells having a threshold voltage equal to or lower than a first verify voltage, from among the memory cells, acquires, in the second erase verify process, the number of second memory cells having a threshold voltage higher than the first verify voltage, from among the first memory cells, and determines whether the number of the second memory cells is larger than a first value or not.

Abstract: A pattern forming method including pressing a mold having an uneven pattern against a curable film formed of a nanoimprint composition to transfer the uneven pattern to the curable film, curing the curable film to which the uneven pattern has been transferred while pressing the mold against the curable film to form a cured film, peeling the mold off from the cured film, and heating the cured film, from which the mold has been peeled off at 160° C. or higher to form a post-baked cured film.

Abstract: A production method for a refined product of a metal nanoparticle-containing composition, including causing a metal nanoparticle-containing composition to pass in a liquid state from one side to the other side of a porous polyimide and/or polyamide-imide membrane having interconnection pores with differential pressure, and a production method for a refined product of a metal nanoparticle dispersion liquid, including causing a metal nanoparticle dispersion liquid to pass from one side to the other side of a porous polyimide and/or polyamide-imide membrane having interconnection pores with differential pressure.

Abstract: A pattern forming method including forming a curable film using a curable composition that contains metal oxide nanoparticles, on a substrate, pressing a mold having a line and space pattern against the curable film to transfer the line and space pattern to the curable film, curing the curable film to which the line and space pattern has been transferred while pressing the mold against the curable film, to form a cured film, and peeling the mold off the cured film to form a line and space pattern on the substrate, in which a line width x of the line and space pattern formed on the substrate in a base portion and a volume average primary particle diameter ? of the metal oxide nanoparticles satisfy an expression of 0.03x<?<0.08x, and an expression of x?500 nm.

Abstract: A photocurable composition including metal oxide nanoparticles, a component (R) which is an unsaturated acid metal salt, a photopolymerizable compound excluding a compound corresponding to the component (R), and a photoradical polymerization initiator.

Abstract: A nanoimprint composition including an unsaturated acid metal salt (R), a photopolymerizable compound (B), a photoradical polymerization initiator, and a solvent component having compatibility with the unsaturated acid metal salt (R) and the photopolymerizable compound (B), in which a content of the unsaturated acid metal salt (R) is 50 parts by mass or greater with respect to 100 parts by mass of a total content of the unsaturated acid metal salt (R) and the photopolymerizable compound (B).

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.

Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.

Abstract: A resistive microfluidic pressure sensor is provided which comprises a first layer comprising a microfluidic channel with a carbon-based conductive liquid and a second layer comprising at least two electrodes, the at least two electrodes being adapted to measure resistance of the carbon-based conductive liquid upon deformation of the microfluidic channel as a result of a change in force applied on a surface of the sensor.

Abstract: The purpose of the present invention is to provide a specific antibody applicable to immunochromatographic detection of Mycoplasma pneumoniae infections, and a detection reagent using the same, among others. Provided are a Mycoplasma pneumoniae detection reagent and kit that include a specific antibody against the P30 protein of Mycoplasma pneumoniae, and an immunochromatographic test device.

Abstract: For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.

Abstract: A resistive microfluidic pressure sensor is provided which comprises a first layer comprising a microfluidic channel with a carbon-based conductive liquid and a second layer comprising at least two electrodes, the at least two electrodes being adapted to measure resistance of the carbon-based conductive liquid upon deformation of the microfluidic channel as a result of a change in force applied on a surface of the sensor.

Abstract: A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a control circuit that executes a write sequence, the write sequence writing data to the memory cells, the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer of 2 or more, write stages, and an initial amplitude and the increment of the program pulse applied in the N?1th write stage being the same as an initial amplitude and the increment of the program pulse applied in the Nth write stage.