Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. The controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. The second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.

Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.

Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform a write operation of a first data cluster and a first partial overwrite operation of the first data cluster with first overwrite data. The write operation includes compressing and then encrypting the first data cluster, and writing the compressed and encrypted first data cluster into a first physical location of the non-volatile memory. The first partial overwrite operation includes encrypting the first overwrite data without performing compression, reading the compressed and encrypted first data cluster from the first physical location of the non-volatile memory, generating a first composite data cluster with the compressed and encrypted first data cluster read from the first physical location and the encrypted first overwrite data that is not compressed, and writing the first composite data cluster into a second physical location of the non-volatile memory.

Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.

Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to segment data into clusters, perform a compression with respect to each of the clusters, allocate the clusters subjected to the compression to encoding frames in accordance with a predetermined rule. According to the predetermined rule, at least a part of a cluster is allocated to a vacant space of an encoding frame in a first state, when a predetermined condition is met, and an entirety of a cluster is allocated to an encoding frame in a second state, when no encoding frame in the first state exists or when the predetermined condition is not met. The controller is further configured to encode data in each of the encoding frames and write the encoded data into the nonvolatile memory.

Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.

Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a movement request from a host, the movement request designating a logical address of movement target data. When update data corresponding to the designated logical address is not written to the nonvolatile memory by a write request from the host in a period from the reception of the movement request to start of movement of data corresponding to the designated logical address, the controller executes a movement process of moving data corresponding to the designated logical address to a movement destination block in the nonvolatile memory. When the update data is written to the nonvolatile memory in the period, the controller does not execute the movement process.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a movement request from a host, the movement request designating a logical address of movement target data. When update data corresponding to the designated logical address is not written to the nonvolatile memory by a write request from the host in a period from the reception of the movement request to start of movement of data corresponding to the designated logical address, the controller executes a movement process of moving data corresponding to the designated logical address to a movement destination block in the nonvolatile memory. When the update data is written to the nonvolatile memory in the period, the controller does not execute the movement process.

Abstract: According to one embodiment, a communication control device includes processing circuitry. The processing circuitry acquires at least either; wired communication characteristic information or wireless communication characteristic information from relaying devices or, storage characteristic information indicating usage of a plurality of storage devices storing data units that are transferred via the relaying devices and sent or received by a terminal in the wireless network or, data characteristic information indicating states of a plurality of data units stored in each of the storage devices. The processing circuitry is configured to receive a data acquisition request or a data saving request sent from the terminal and specify a relaying device or a storage device that processes the data acquisition request or the data saving request, and sends an instruction to the terminal, instructing to transmit the data acquisition request or the data saving request to the specified relaying device or the storage device.

Abstract: The data transfer device receives file data through a network and writes the file data to a storage device on a block basis, in which the communication processor receives a receiving instruction for the file data from an external host CPU and receives the file data via one or more packets from the network according to the receiving instruction, the receiving buffer stores data received in the communication processor therein upon receiving each packet, and the command issuance controller acquires, from the external host CPU, map information indicating a position to write the file data in a storage area of the storage device, specifies data in the receiving buffer for writing according to a data storing status of the receiving buffer, issues a write command for writing a specified data to the storage device and sends it to the storage device.

Abstract: A communication device includes: processing circuitry and communication circuitry. The processing circuitry acquires first information related to one or more pieces of content cached in each of relay devices being capable of communicating with a server and are capable of exchanging any of the pieces of content cached therein with one another. The processing circuitry acquires a first content list including an identifier of each of a plurality of pieces of content stored in the server. The processing circuitry specifies, on a basis of the first information, an identifier of a piece of content cached in at least one of the relay devices among the first content list and generates a second content list including the specified identifier and second information indicating that the piece of content identified by the specified identifier is cached in at least one of the relay devices. The communication circuitry transmits the second content list.

Abstract: According to one embodiment, a communication control device includes processing circuitry. The processing circuitry acquires at least either; wired communication characteristic information or wireless communication characteristic information from relaying devices or, storage characteristic information indicating usage of a plurality of storage devices storing data units that are transferred via the relaying devices and sent or received by a terminal in the wireless network or, data characteristic information indicating states of a plurality of data units stored in each of the storage devices. The processing circuitry is configured to receive a data acquisition request or a data saving request sent from the terminal and specify a relaying device or a storage device that processes the data acquisition request or the data saving request, and sends an instruction to the terminal, instructing to transmit the data acquisition request or the data saving request to the specified relaying device or the storage device.

Abstract: According to one embodiment, a network device includes a receiver, a processor and a transmitter. The receiver receives a delivery reservation request of content from a first terminal in a coverage area of the network device. The processor selects a first network device from among a plurality of other network devices on the basis of the delivery reservation request, the other network devices being wirelessly communicable with terminals in respective coverage areas. The transmitter transmits a cache request to the first network device, the cache request instructing to acquire and cache the content from a content provision device. The transmitter transmits first information to the first terminal, the first information being information required to acquire the content from the first network device.

Abstract: A communication device includes: processing circuitry and communication circuitry. The processing circuitry acquires first information related to one or more pieces of content cached in each of relay devices being capable of communicating with a server and are capable of exchanging any of the pieces of content cached therein with one another. The processing circuitry acquires a first content list including an identifier of each of a plurality of pieces of content stored in the server. The processing circuitry specifies, on a basis of the first information, an identifier of a piece of content cached in at least one of the relay devices among the first content list and generates a second content list including the specified identifier and second information indicating that the piece of content identified by the specified identifier is cached in at least one of the relay devices. The communication circuitry transmits the second content list.

Abstract: According to one embodiment, there is provided a storage controlling device including a receiving unit and a controlling unit. The receiving unit receives a read command or a write command for a storage device, from an internal or external command issuing device. The controlling unit holds the write command received by the receiving unit until at least a first interval time has elapsed after outputting a write command received most recently before the write command is received, and then outputs the write command which is held after the first interval time has elapsed. The controlling unit outputs the read command received by the receiving unit, prior to outputting the write command that is held, when the read command is received during a time when the write command is held.

Abstract: According to one embodiment, a communication device includes a communication processor configured to execute at least one of transmission processing and reception processing of a packet; a writer circuitry configured to write data included in the packet to a buffer; a reader circuitry configured to read the data from the buffer; and processing circuitry configured to stop at least part of the write to the buffer, change the buffer after the buffer becomes empty, and restart the write to the changed buffer.

Abstract: According to one embodiment, a data storage device includes: a first hardware storage device; a second hardware storage device in which write is done by an integer multiple size of a predetermined size. The data storage device writes data into the first hardware storage device in response to a write instruction of data having expiration information. The data storage device manages data management information including: the expiration information of data written into the first hardware storage device; and a storage location of the data. The data storage device selects, when a predetermined condition is satisfied, a plurality of pieces of data in the first hardware storage device based on temporal proximity among pieces of the expiration information, reads out the pieces of data from the first hardware storage device, and writes the pieces of data into the second hardware storage device.

Abstract: According to one embodiment, a communication device including: a network interface configured to receive a frame from a client; first circuitry configured to determine whether or not the frame is a cache target which requires same content a predetermined number of times or more within a predetermined time period; and second circuitry configured to cache the content required by the frame in a case where the frame is the cache target.