Abstract: A semiconductor device capable of monitoring a connection state of a terminal on a semiconductor chip includes a selector configured to acquire terminal levels of a plurality of respective terminals on the semiconductor chip to which an inspection pattern is inputted based on a detection signal, a memory configured to store latch data based on a chip address which identifies the semiconductor chip and a plurality of the terminal levels corresponding to the plurality of terminals based on the detection signal, an output circuit configured to read a plurality of pieces of latch data from the memory based on the detection signal and to output the plurality of pieces of latch data, and a timing control circuit configured to generate the detection signal by detecting an edge of a clock inputted during an inspection mode and configured to activate the selector, the memory, and the output circuit.

Abstract: A semiconductor device capable of monitoring a connection state of a terminal on a semiconductor chip includes a selector configured to acquire terminal levels of a plurality of respective terminals on the semiconductor chip to which an inspection pattern is inputted based on a detection signal, a memory configured to store latch data based on a chip address which identifies the semiconductor chip and a plurality of the terminal levels corresponding to the plurality of terminals based on the detection signal, an output circuit configured to read a plurality of pieces of latch data from the memory based on the detection signal and to output the plurality of pieces of latch data, and a timing control circuit configured to generate the detection signal by detecting an edge of a clock inputted during an inspection mode and configured to activate the selector, the memory, and the output circuit.

Abstract: A semiconductor device capable of monitoring a connection state of a terminal on a semiconductor chip includes a selector configured to acquire terminal levels of a plurality of respective terminals on the semiconductor chip to which an inspection pattern is inputted based on a detection signal, a memory configured to store latch data based on a chip address which identifies the semiconductor chip and a plurality of the terminal levels corresponding to the plurality of terminals based on the detection signal, an output circuit configured to read a plurality of pieces of latch data from the memory based on the detection signal and to output the plurality of pieces of latch data, and a timing control circuit configured to generate the detection signal by detecting an edge of a clock inputted during an inspection mode and configured to activate the selector, the memory, and the output circuit.

Abstract: According to one embodiment, a semiconductor device includes a board, a plurality of external connection terminals, a semiconductor component, and an insulator. The board includes a first surface and a second surface. The second surface is located on a side opposite to the first surface. The plurality of external connection terminals is on the first surface. The semiconductor component is located on a side opposite to the plurality of external connection terminals with respect to the board. The insulator includes a first region and a second region. The first region has a first thickness in a thickness direction of the board. The second region is located on an outer peripheral side of the first region and has a second thickness thinner than the first thickness in the thickness direction. The insulator covers the semiconductor component from a side opposite to the board.

Abstract: A semiconductor device capable of monitoring a connection state of a terminal on a semiconductor chip includes a selector configured to acquire terminal levels of a plurality of respective terminals on the semiconductor chip to which an inspection pattern is inputted based on a detection signal, a memory configured to store latch data based on a chip address which identifies the semiconductor chip and a plurality of the terminal levels corresponding to the plurality of terminals based on the detection signal, an output circuit configured to read a plurality of pieces of latch data from the memory based on the detection signal and to output the plurality of pieces of latch data, and a timing control circuit configured to generate the detection signal by detecting an edge of a clock inputted during an inspection mode and configured to activate the selector, the memory, and the output circuit.