Abstract: A presettable dynamic delay flip-flop circuit including two first and second series-connected 1/2 bit delay circuits, a gate circuit for supplying these delay circuits with a control signal for controlling their operation, and a switching circuit for supplying the second delay circuit with preset data capable of freely presetting the voltage level of an output signal from said flip-flop circuit. The delay circuits and switching circuit are respectively formed of clocked inverters. The flip-flop circuit is formed of a small number of elements and operated at high frequency.

Abstract: A ROM with a matrix array of insulated gate enhancement type field effect transistors in each of which any information is not yet written is preliminarily prepared by a plurality of strip-shape diffusion regions doped at a predetermined interval in a given conductivity type semiconductor substrate and having a conductivity type opposite to that of the substrate, a plurality of strip-shape electroconductive metal layers formed through a first relatively thick insulation layer on the substrate at a predetermined interval so as to intersect the respective diffusion regions; and a plurality of gate electrode foils each formed through a second insulation layer thinner than the first insulation layer on that surface portion of the substrate which positions between the corresponding mutually facing ones of the diffusion regions so as integrally to project from the corresponding one of the electroconductive metal layers.

Abstract: A counter comprises a cascade connection of an inverter stage and n one-bit shift register stages, the latter being operative in response to clock signals to be counted and each having a data-readin or front half-bit shift register stage and a data-readout or rear half-bit shift register stage. The output of the final stage in the cascade connection is coupled to the input of the first stage in the cascade connection. The output of the final stage is also coupled to an additional input of consecutive 1st to X-th shift register stages or consecutive 2nd to (X-1)-th shift register stages of an X-th shift register stage to constitute a scale-of-2n-X or 2n-(X-1) counter.

Abstract: An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplied with pulses to be counted and each of the delay cicuits is set or reset to an initial state. There is also provided a closed loop circuit including a first gate circuit connected to receive an output signal from the last stage delay circuit as one input terminal, and a logic circuit connected to receive output signals from the first gate circuit and, for example, the first stage delay circuit and produce to the input terminal of the first stage delay circuit an output signal indicating coincidence or incoincidence of its input signals. The counter is capable of counting pulses of (2.sup.x -1) at maximum.

Abstract: A series logic circuit arrangement using a plurality of complementary IGFET's and comprising a plurality of series connected logic circuits, each of the logic circuits being designed to effect a predetermined logic function with respect to input binary coded signals by using at least one P channel IGFET and one N channel IFGET. In the negative logic system, the P channel IGFET's are arranged on a semiconductor substrate according to a logic equation of minterm-type expression, and the N channel IGFET's are arranged on the substrate according to a logic equation of maxterm-type expression, and, in the positive logic system, the N channel IGFET's are provided on the substrate according to the logic equation of minterm-type expression, and the P channel IGFET's are disposed on the substrate according to the logic equation of maxterm-type expression, thereby admitting of integrating the P and N channel IGFET's on the substrate within a smallest possible area.