Patents by Inventor Kenshi Tsuchiya

Kenshi Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120162547
    Abstract: According to one embodiment, a video display device includes a housing, a display module, a wall portion, a first circuit board and a second circuit board. The housing houses at least part of the display module. The wall portion is located opposite the display screen with respect to the display module. The first circuit board includes an input signal processing circuit that outputs at least video data from an input signal. The second circuit board includes a frame rate converter circuit and a timing control circuit. The frame rate converter circuit generates an interpolation frame based on frames of the video data received from the input signal processing circuit and outputs the video data with an increased frame rate. The timing control circuit outputs a timing control signal to a driver circuit that drives the display module based on the video data received from the frame rate converter circuit.
    Type: Application
    Filed: November 18, 2011
    Publication date: June 28, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kenshi Tsuchiya
  • Patent number: 7452118
    Abstract: Area light source 10 used for LCD device 1 includes light guide 12 and LED devices 18 and 19 disposed at a side portion of light guide 12. A light receiving portion at a side edge portion of light guide 12 is provided with prisms 24 and 25 of saw-tooth prism group 22. Apex angles of prisms 24 and 25 are set to be more acute up to the middle point of prisms 24 and 25 as prisms 24 and 25 are farther from LED devices 18 and 19, respectively.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: November 18, 2008
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Kenshi Tsuchiya
  • Patent number: 7425728
    Abstract: A surface light source control device has a plane light source control circuit for setting a current amount to a plurality of diode arrays. The light source control circuit comprises a constant current circuit for holding currents respectively flowing in the plurality of diode arrays constant at the same current value; and a power supply voltage control loop for selecting a notable diode array with a minimum reference voltage, among reference voltages appearing at each terminal of the plurality of diode arrays, appeared thereon to select the minimum reference voltage by a voltage selection circuit and adjusting a common power supply voltage so that the reference voltage becomes a prescribed value.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: September 16, 2008
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Kenshi Tsuchiya
  • Publication number: 20060238367
    Abstract: Area light source 10 used for LCD device 1 includes light guide 12 and LED devices 18 and 19 disposed at a side portion of light guide 12. A light receiving portion at a side edge portion of light guide 12 is provided with prisms 24 and 25 of saw-tooth prism group 22. Apex angles of prisms 24 and 25 are set to be more acute up to the middle point of prisms 24 and 25 as prisms 24 and 25 are farther from LED devices 18 and 19, respectively.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 26, 2006
    Applicant: Toshiba Matsushita Display Technology
    Inventor: Kenshi Tsuchiya
  • Publication number: 20060139299
    Abstract: A surface light source control device has a plane light source control circuit for setting a current amount to a plurality of diode arrays. The light source control circuit comprises a constant current circuit for holding currents respectively flowing in the plurality of diode arrays constant at the same current value; and a power supply voltage control loop for selecting a notable diode array with a minimum reference voltage, among reference voltages appearing at each terminal of the plurality of diode arrays, appeared thereon to select the minimum reference voltage by a voltage selection circuit and adjusting a common power supply voltage so that the reference voltage becomes a prescribed value.
    Type: Application
    Filed: November 21, 2005
    Publication date: June 29, 2006
    Inventor: Kenshi Tsuchiya
  • Patent number: 6256003
    Abstract: A jitter correction circuit includes a delayed signal generator and an output circuit. A correction subject signal Ckd0 is derived from multiplying a horizontal synchronization signal or a reference signal Vref. The correction subject signal includes jitters. The delayed signal generator is provided with a plurality of delay elements Fd1 through Fdn which receive and delay the correction subject signal, respectively, by predetermined delay time to generate delayed signals Ckd1 through Ckdn. The output circuit outputs one of the correction subject signal Ckd0 and the delayed signals Ckd1 trough Ckdn on the condition that it has predetermined timing relationship with the reference signal Vref.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: July 3, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenshi Tsuchiya, Hirofumi Kato, Hiroyoshi Murata
  • Patent number: 5874933
    Abstract: A multi-gradation liquid crystal display having dual display definition modes that can display both TV pictures and office automation images, both without flicker. Scanning electrodes extend in a first direction. Scanning and non-scanning voltages are selectively applied to the scanning electrodes. Signal electrodes extend in a second direction perpendicular to the first direction. First and second signal voltages are selectively applied to the signal electrodes. A layer of liquid crystal is sandwiched between the scanning and signal electrodes. Mode switching is provided for switching display between a first mode wherein an image is displayed by two-gradation pixels and a second mode wherein an image is displayed by three or more gradation pixels.
    Type: Grant
    Filed: August 25, 1995
    Date of Patent: February 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hoko Hirai, Masaki Miyatake, Kenshi Tsuchiya, Seiichi Sagi