Patents by Inventor Kensho Murata
Kensho Murata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7282175Abstract: A lead-free solder includes 0.05-5 mass % of Ag, 0.01-0.5 mass % of Cu, at least one of P, Ge, Ga, Al, and Si in a total amount of 0.001-0.05 mass %, and a remainder of Sn. One or more of a transition element for improving resistance to heat cycles, a melting point lowering element such as Bi, In, or Zn, and an element for improving impact resistance such as Sb may be added.Type: GrantFiled: April 15, 2004Date of Patent: October 16, 2007Assignee: Senju Metal Industry Co., Ltd.Inventors: Masazumi Amagai, Masako Watanabe, Kensho Murata, Yoshitaka Toyoda, Minoru Ueshima, Tsukasa Ohnishi, Takeshi Tashima, Daisuke Souma, Takahiro Roppongi, Hiroshi Okada
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Patent number: 7029542Abstract: A lead-free solder alloy comprises 1.0–5.0 wt % Ag, 0.01–0.5 wt % Ni, one or both of (a) 0.001–0.05 wt % Co and (b) at least one of P, Ge, and Ga in a total amount of 0.001–0.05 wt %, and a remainder of Sn. The solder can form solder bumps which have a high bonding strength and which do not undergo yellowing after soldering.Type: GrantFiled: July 8, 2003Date of Patent: April 18, 2006Assignee: Senju Metal Industry Co., Ltd.Inventors: Masazumi Amagai, Masako Watanabe, Kensho Murata, Osamu Munekata, Yoshitaka Toyoda, Minoru Ueshima, Tsukasa Ohnishi, Hiroshi Okada
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Patent number: 6965162Abstract: A semiconductor device designed to reduce the warp of a substrate due to curing contraction, etc. of an insulation pattern while forming the insulation pattern on the surface of a substrate so that it may be interposed between a semiconductor chip and a conductor pattern by offering a semiconductor chip mounting substrate equipped with a flexible substrate 11 (insulating film 16) having a chip mounting region 19 for mounting a semiconductor chip 13 via an adhesive 12, conductor patterns 20 that are formed on the surface of the above-mentioned substrate 11 and electrically connected to the semiconductor chip 13 in an external region of the above-mentioned chip mounting region 19, and an insulation pattern 21 formed on the surface of the substrate 11 and partially in the chip mounting region 19 so that it may be interposed between the semiconductor chip 13 and the conductor patterns 20.Type: GrantFiled: August 23, 2002Date of Patent: November 15, 2005Assignee: Texas Instruments IncorporatedInventors: Makoto Yoshino, Kunio Sakamoto, Kensho Murata
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Patent number: 6929971Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.Type: GrantFiled: November 22, 2002Date of Patent: August 16, 2005Assignee: Texas Instruments IncorporatedInventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
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Patent number: 6876077Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.Type: GrantFiled: January 17, 2003Date of Patent: April 5, 2005Assignee: Texas Instruments IncorporatedInventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
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Publication number: 20040262779Abstract: A lead-free solder includes 0.05-5 mass % of Ag, 0.01-0.5 mass % of Cu, at least one of P, Ge, Ga, Al, and Si in a total amount of 0.001-0.05 mass %, and a remainder of Sn. One or more of a transition element for improving resistance to heat cycles, a melting point lowering element such as Bi, In, or Zn, and an element for improving impact resistance such as Sb may be added.Type: ApplicationFiled: April 15, 2004Publication date: December 30, 2004Inventors: Masazumi Amagai, Masako Watanabe, Kensho Murata, Yoshitaka Toyoda, Minoru Ueshima, Tsukasa Ohnishi, Takeshi Tashima, Daisuke Souma, Takahiro Roppongi, Hiroshi Okada
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Publication number: 20030155652Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.Type: ApplicationFiled: November 22, 2002Publication date: August 21, 2003Inventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
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Publication number: 20030107054Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.Type: ApplicationFiled: January 17, 2003Publication date: June 12, 2003Inventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
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Publication number: 20030039102Abstract: A semiconductor device designed to reduce the warp of a substrate due to curing contraction, etc. of an insulation pattern while forming the insulation pattern on the surface of a substrate so that it may be interposed between a semiconductor chip and a conductor pattern by offering a semiconductor chip mounting substrate equipped with a flexible substrate 11 (insulating film 16) having a chip mounting region 19 for mounting a semiconductor chip 13 via an adhesive 12, conductor patterns 20 that are formed on the surface of the above-mentioned substrate 11 and electrically connected to the semiconductor chip 13 in an external region of the above-mentioned chip mounting region 19, and an insulation pattern 21 formed on the surface of the substrate 11 and partially in the chip mounting region 19 so that it may be interposed between the semiconductor chip 13 and the conductor patterns 20.Type: ApplicationFiled: August 23, 2002Publication date: February 27, 2003Inventors: Makoto Yoshino, Kunio Sakamoto, Kensho Murata
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Patent number: 6525424Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.Type: GrantFiled: April 4, 2001Date of Patent: February 25, 2003Assignee: Texas Instruments IncorporatedInventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
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Publication number: 20020145198Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.Type: ApplicationFiled: April 4, 2001Publication date: October 10, 2002Inventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
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Patent number: 6087717Abstract: To completely suppress or minimize the voids formed between the insulating substrate and the IC chip in order to prevent the problems of separation and cracking of the chip caused by the aforementioned voids. The present invention is preferably adopted for the Chip Six Package type package or other package types equipped with solder bumps or other external connecting terminals directly beneath the IC chip. For insulating substrate (3), on its chip-carrying surface, there is pattern element (6) in the region beneath the IC chip and free of conductor pattern elements (4) in addition to conductor pattern element (4) for forming electrical connection between the electrode pads and the external connecting terminals of the chip. Said pattern element (6) divides said region into plural small regions A. IC chip (2) is bonded through die paste on insulating substrate (3) such that an end of conductor pattern element (4), pattern element (6) and divided small regions A are covered.Type: GrantFiled: March 23, 1998Date of Patent: July 11, 2000Assignee: Texas Instruments IncorporatedInventors: Kazuaki Ano, Kensho Murata