Abstract: Provided is a manufacturing method of a semiconductor device having a semiconductor substrate. The manufacturing method includes forming an interlayer insulating film above the semiconductor substrate; forming a metal electrode above the interlayer insulating film; acquiring an image of the metal electrode and detecting defect candidates on a surface of the metal electrode based on the image; and performing inspection by determining a quality of the semiconductor device, based on height information of each of the detected defect candidates in a direction perpendicular to the surface of the metal electrode.

Abstract: A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide semiconductor substrate in which, on a front surface of a starting substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the starting substrate. Next, at the surface of the first semiconductor layer, a second semiconductor layer of a second conductivity type is formed. Next, at the surface of the second semiconductor layer, an ohmic electrode is formed. Next, at the surface of the ohmic electrode, a Ti film and a TiN film are sequentially deposited to form a barrier metal. Next, the barrier metal is subjected to a heat treatment to form an annealed barrier metal. The heat treatment is performed in a range of 550 degrees C. to 750 degrees C.

Abstract: A silicon carbide semiconductor device has a semiconductor substrate, a trench gate structure disposed in the semiconductor substrate, a first electrode electrically connected to an impurity region and a bae layer of the semiconductor substrate, a second electrode connected to a substrate, and an interlayer insulating film disposed between a gate electrode and the first electrode. The trench gate structure includes a gate insulating film disposed in a trench of the semiconductor substrate and the gate electrode disposed on the gate insulating film. A portion of the semiconductor substrate adjoining the trench has a termination structure in which dangling bonds are terminated with at least one of nitrogen, hydrogen or phosphorous. The interlayer insulating film has a contact insulating film that is in contact with the gate electrode. The contact insulating film is provided by a deposited film.

Abstract: Provided is a manufacturing method of a semiconductor device having a semiconductor substrate. The manufacturing method includes forming an interlayer insulating film above the semiconductor substrate; forming a metal electrode above the interlayer insulating film; acquiring an image of the metal electrode and detecting defect candidates on a surface of the metal electrode based on the image; and performing inspection by determining a quality of the semiconductor device, based on height information of each of the detected defect candidates in a direction perpendicular to the surface of the metal electrode.

Abstract: A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.

Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.

Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.

Abstract: A load sensor is constituted by a rib and a vertical transistor including an organic semiconductor film, and a load measurement can be executed based on a change of a gap between a drain electrode and a source electrode which is a channel length of the vertical transistor. Therefore, a change of a current Ids is in a linear relationship to a load applied to the load sensor.

Abstract: A load sensor is constituted by a rib and a vertical transistor including an organic semiconductor film, and a load measurement can be executed based on a change of a gap between a drain electrode and a source electrode which is a channel length of the vertical transistor. Therefore, a change of a current Ids is in a linear relationship to a load applied to the load sensor.