Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: According to one embodiment, a storage device comprises a memory cell, a control circuit, and a command register. The memory cell array is configured to store data. The control circuit is configured to process the data stored in the memory cell array in accordance with a command transmitted from a controller. The command register is configured to store a first command and a second command transmitted from the controller.

Abstract: An information processing system includes a transmission device configured to sequentially transmit a first packet and a second packet containing data to be stored in contiguous logical addresses of a destination device, to the transmission destination device. The first packet includes a first header, and the second packet includes a second header smaller in size than the first header.

Abstract: An information processing system includes a transmission device configured to sequentially transmit a first packet and a second packet containing data to be stored in contiguous logical addresses of a destination device, to the transmission destination device. The first packet includes a first header, and the second packet includes a second header smaller in size than the first header.