Patents by Inventor Kensuke Okonogi
Kensuke Okonogi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9236387Abstract: A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.Type: GrantFiled: February 21, 2014Date of Patent: January 12, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Kiyonori Oyu, Kensuke Okonogi, Kazuto Mori
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Publication number: 20140167125Abstract: A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Applicant: Elpida Memory, Inc.Inventors: Kiyonori OYU, Kensuke OKONOGI, Kazuto MORI
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Patent number: 8704299Abstract: A semiconductor device capable of increasing ON current while reducing channel resistance and allowing transistors to operate independently and stably, having a fin formed to protrude from the bottom of a gate electrode trench, a gate insulating film covering the surfaces of the gate electrode trench and the fin, a gate electrode embedded in a lower part of the gate electrode trench and formed to stride over the fin via the gate insulating film, a first impurity diffusion region arranged on a first side face, and a second impurity diffusion region arranged on a second side face.Type: GrantFiled: January 8, 2013Date of Patent: April 22, 2014Inventors: Kiyonori Oyu, Kensuke Okonogi, Kazuto Mori
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Patent number: 8674455Abstract: A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 ?m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.Type: GrantFiled: December 22, 2011Date of Patent: March 18, 2014Inventors: Kensuke Okonogi, Kazuhiro Nojima, Kiyonori Oyu
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Publication number: 20120305999Abstract: Provided are a semiconductor device capable of increasing an ON current with a reduced channel resistance, and also capable of stably and independently operating respective transistors, and a method of manufacturing the semiconductor device. A semiconductor device includes a fin portion located in a manner that a part of an active region protrudes from a bottom portion of a gate groove, a gate insulating film for covering the gate groove and a surface of the fin portion, a gate electrode which is embedded within a lower portion of the gate groove and formed so as to straddle the fin portion via the gate insulating film, a first diffusion region, a second diffusion region, and a carrier capture region provided in the surface of the fin portion.Type: ApplicationFiled: May 31, 2012Publication date: December 6, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Kensuke OKONOGI
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Publication number: 20120161219Abstract: a semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 ?m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.Type: ApplicationFiled: December 22, 2011Publication date: June 28, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Kensuke OKONOGI, Kazuhiro NOJIMA, Kiyonori OYU
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Patent number: 7846826Abstract: A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.Type: GrantFiled: October 7, 2008Date of Patent: December 7, 2010Assignee: Elpida Memory Inc.Inventors: Kiyonori Oyu, Kensuke Okonogi
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Publication number: 20100302888Abstract: A memory cell potentially including a retention fault attributable to a random change over time of data retention capability is screened by applying a bias to a gate electrode such that holes are accumulated on an interface of a substrate that is a component of a memory cell transistor on the side of the gate electrode and, after applying the bias, performing a pause-refresh test for inspecting the data retention capability of the memory cell.Type: ApplicationFiled: May 27, 2010Publication date: December 2, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Yuki MORI, Kensuke OKONOGI, Shuichi TSUKADA
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Patent number: 7737505Abstract: A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.Type: GrantFiled: September 21, 2007Date of Patent: June 15, 2010Assignee: Elpida Memory, Inc.Inventors: Kensuke Okonogi, Kiyonori Ohyu
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Patent number: 7700431Abstract: A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.Type: GrantFiled: June 16, 2005Date of Patent: April 20, 2010Assignee: Elpida Memory, Inc.Inventors: Kensuke Okonogi, Kiyonori Ohyu, Kazutaka Manabe, Satoru Yamada, Takuo Ohashi
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Patent number: 7666761Abstract: In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.Type: GrantFiled: March 1, 2007Date of Patent: February 23, 2010Assignee: Elpida Memory, Inc.Inventors: Kiyonori Oyu, Kensuke Okonogi, Hirotaka Kobayashi, Koji Hamada
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Patent number: 7632696Abstract: A semiconductor chip including a semiconductor substrate provided with a semiconductor device region and a porous single crystal layer, where the semiconductor device region is formed on the main surface portion of the semiconductor substrate, and the porous single crystal layer is formed in an inner region on the backside of the semiconductor substrate, and is comprised of erosion holes extending continuously from the backside of the semiconductor substrate in an inward direction of the semiconductor substrate, oxide films formed on inner surfaces of the erosion holes, and a single crystal portion.Type: GrantFiled: March 10, 2006Date of Patent: December 15, 2009Assignee: Elpida Memory, Inc.Inventors: Kiyonori Oyu, Koji Hamada, Kensuke Okonogi, Hideharu Miyake, Yasushi Kozuki, Masaharu Watanabe
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Publication number: 20090209079Abstract: A method for manufacturing a semiconductor device includes forming a diffusion layer on a silicon substrate by doping an impurity of a first conductivity type into a region of a second conductivity type opposite to the first conductivity type and performing a heat treatment; implanting nitrogen or fluorine ions into the diffusion layer; and irradiating carbon dioxide gas laser light to the diffusion layer after the implanting.Type: ApplicationFiled: January 21, 2009Publication date: August 20, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Kiyonori OYU, Kensuke Okonogi, Akio Shima
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Publication number: 20090042380Abstract: A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.Type: ApplicationFiled: October 7, 2008Publication date: February 12, 2009Applicant: Elpida Memory, Inc.Inventors: Kiyonori OYU, Kensuke OKONOGI
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Publication number: 20080230845Abstract: A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor.Type: ApplicationFiled: September 21, 2007Publication date: September 25, 2008Applicant: ELPIDA MEMORY, INCInventors: Kensuke Okonogi, Kiyonori Ohyu
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Publication number: 20080061339Abstract: A semiconductor device includes a single-crystal semiconductor substrate; and a stress applying device for applying a desired mess to specific one or more parts on or in the single-crystal semiconductor substrate. Typically, the stress applying device includes a capacitance element, which is arranged in the vicinity of the specific one or more parts, and has a dielectric made of an electrostrictive material; and a device for applying a voltage in a direction parallel to a polarization vector of the dielectric. The specific one or more parts may be one or more p-n junctions, each of which may be included in a MOS transistor. In this case, each MOS transistor may function as a redundant cell or a main cell for forming a DRAM. The desired stress may be applied in a predetermined direction, and may have an amount for applying a desired distortion to the specific one or more parts.Type: ApplicationFiled: September 7, 2007Publication date: March 13, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Kensuke OKONOGI, Kiyonori OHYU
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Patent number: 7338876Abstract: A method for forming a semiconductor memory device includes the steps of: implanting a dopant in a semiconductor substrate; heat treating the semiconductor substrate in an oxidizing ambient to diffuse the dopant for forming diffused regions in the semiconductor substrate; and forming memory cells each including a MOS transistor having the diffused regions as source/drain regions.Type: GrantFiled: January 24, 2005Date of Patent: March 4, 2008Assignee: Elpida Memory, Inc.Inventors: Kensuke Okonogi, Kiyonori Oyu
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Publication number: 20070158784Abstract: In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.Type: ApplicationFiled: March 1, 2007Publication date: July 12, 2007Inventors: Kiyonori Oyu, Kensuke Okonogi, Hirotaka Kobayashi, Koji Hamada
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Publication number: 20070092993Abstract: A semiconductor device manufacture method includes: bonding a main device surface of a semiconductor chip onto a package tape with adhesive material; and subjecting the semiconductor chip and the package tape to baking to cure the adhesive material. The baking of the semiconductor chip and the package tape is accompanied by supplying blow gas to a rear surface of the semiconductor chip.Type: ApplicationFiled: October 19, 2006Publication date: April 26, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Kiyonori Oyu, Kensuke Okonogi
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Patent number: 7186632Abstract: In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2×1020(1/cm3) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.Type: GrantFiled: March 24, 2003Date of Patent: March 6, 2007Assignee: Elpida Memory, Inc.Inventors: Kazuo Ogawa, Kiyonori Ohyu, Kensuke Okonogi, Toshihiro Imamura, Keiichi Watanabe, Hiroyuki Ohta