Abstract: A substrate processing condition setting method includes acquiring, causing, and setting. In the acquiring, a plurality of estimation processing results are acquired by inputting a plurality of processing conditions to a trained model that is subjected to machine training based on a training processing condition and a processing result obtained by processing a substrate under the training processing condition. In the causing, a display section is caused to display an image based on the estimation processing results. In the setting, one processing condition corresponding to one estimation processing result of the estimation processing results is set, as an actual processing condition in substrate processing, based on the image displayed on the display section.

Abstract: In order to improve the quality of a substrate, a substrate processing apparatus includes a substrate holding unit, a first drive unit, a chemical liquid discharge portion, a cup unit, a second drive unit, and a control unit. The substrate holding unit holds a substrate having a first surface and a second surface opposite to the first surface in a horizontal posture. The first drive unit rotates the substrate holding unit about a virtual axis. The chemical liquid discharge portion discharges a chemical liquid toward the first surface of the substrate held by the substrate holding unit. The cup unit surrounds a periphery of the substrate holding unit. The second drive unit changes a relative position in the vertical direction of the cup unit with respect to the substrate holding unit.

Abstract: A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line.

Abstract: A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line.

Abstract: A semiconductor memory device includes a first memory circuits connecting to a first bit line, a second bit line and a word line, a first pre-charge control circuit connecting to a first pre-charge control line, the first bit line and the second bit line and that pre-charges the first bit line and the second bit line on the basis of the input from the first pre-charge control line, and a read control circuit having a first transistor, a second transistor, a third transistor and a fourth transistor, wherein the fourth transistor is brought into conduction on the basis of the input from a charged global-bit-line driver control line, the column having the first bit line and the second bit line is thus selected, and the information held in the memory circuit connecting to the driven word line among the memory circuits is output to the third bit line.

Abstract: A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a predetermined value, when the pulse signal indicates a specific process variation, by using a transistor of which a channel width and a gate length are set to an unbalanced state, and outputs the predetermined value.

Abstract: A process variation detector includes a pulse-signal generating unit that generates a pulse signal having a pulse width corresponding to a characteristic of a process variation in an integrated circuit based on a clock signal; and an output unit that generates a predetermined value, when the pulse signal indicates a specific process variation, by using a transistor of which a channel width and a gate length are set to an unbalanced state, and outputs the predetermined value.

Abstract: An optical repeater having a first optical fiber extending from an input optical fiber cable, a light amplifying medium connected to the first optical fiber, a pumping light source for outputting pumping light, an optical coupling module for introducing the pumping light into the light amplifying medium, a drive circuit for driving the pumping light source, a power circuit for supplying electric power to the drive circuit, and a second optical fiber for sending signal light amplified. The optical repeater has a general-purpose common frame. The common frame has an inner space defined so as to accommodate the pumping light source and the optical coupling module, and has a bobbin portion for winding at least one of the first optical fiber and the second optical fiber. The drive circuit and the power circuit sometimes differing according to the kinds of products are mounted on an individual frame detachably fixed to the common frame.