Patents by Inventor Kensuke Takano

Kensuke Takano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9368719
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: June 14, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Publication number: 20150171318
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
    Type: Application
    Filed: December 12, 2014
    Publication date: June 18, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8941088
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8829593
    Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Kensuke Takano, Masaaki Higuchi, Tetsuya Kai, Yoshio Ozawa
  • Publication number: 20140021430
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
    Type: Application
    Filed: September 27, 2013
    Publication date: January 23, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8569728
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8530876
    Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa
  • Patent number: 8450715
    Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa, Ryota Fujitsuka, Mitsuru Sato
  • Patent number: 8253189
    Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
  • Publication number: 20120186604
    Abstract: According to one embodiment, a cleaning gas is sealed in a chamber of a semiconductor manufacturing apparatus, and the cleaning gas and deposits adhered in the chamber are reacted with each other to generate a reactive gas. After a predetermined time, the gas is exhausted from the chamber. Then, the chamber is evacuated while the cleaning gas is introduced into the chamber, and the reactive gas concentration contained in an exhausted gas is measured. The reactive gas concentration is compared with a determination value obtained when the deposits are removed from the chamber to determine whether the cleaning is terminated.
    Type: Application
    Filed: September 15, 2011
    Publication date: July 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kensuke Takano, Shinji Miyazaki, Ken Ishii, Takashi Nakao
  • Patent number: 8089121
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: January 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Masaru Kito
  • Publication number: 20110193050
    Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.
    Type: Application
    Filed: September 17, 2010
    Publication date: August 11, 2011
    Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa
  • Publication number: 20110068316
    Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 24, 2011
    Inventors: Kensuke TAKANO, Katsuyuki Sekine, Yoshio Ozawa, Ryota Fujitsuka, Mitsuru Sato
  • Publication number: 20100314602
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer
    Type: Application
    Filed: March 22, 2010
    Publication date: December 16, 2010
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Publication number: 20100237402
    Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
    Type: Application
    Filed: March 18, 2010
    Publication date: September 23, 2010
    Inventors: Katsuyuki SEKINE, Kensuke TAKANO, Masaaki HIGUCHI, Tetsuya KAI, Yoshio OZAWA
  • Publication number: 20100123180
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.
    Type: Application
    Filed: September 22, 2009
    Publication date: May 20, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kensuke TAKANO, Yoshio Ozawa, Katsuyuki Sekine, Masaru Kito
  • Publication number: 20100019312
    Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.
    Type: Application
    Filed: July 28, 2009
    Publication date: January 28, 2010
    Inventors: Katsuyuki SEKINE, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
  • Patent number: 7615500
    Abstract: A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: November 10, 2009
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Kensuke Takano, Ichiro Yamamoto, Koji Watanabe
  • Publication number: 20070212898
    Abstract: A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 13, 2007
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Kensuke Takano, Ichiro Yamamoto, Koji Watanabe