Patents by Inventor Kensuke Takano
Kensuke Takano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240116407Abstract: A vehicle seat includes a hinge cover that is disposed at aside portion of a seat cushion and has an opening through which a recliner shaft of a recliner provided between the seat cushion and a seat back passes, and a reclining lever that is disposed at an outer side in a seat width direction with respect to the hinge cover and is rotatable about the recliner shaft to unlock the recliner. A part of an edge portion of the opening of the hinge cover is provided with a facing portion that protrudes further toward the recliner shaft side than another portion of the edge portion and faces the recliner shaft in proximity.Type: ApplicationFiled: October 9, 2023Publication date: April 11, 2024Inventors: Yukinori MIKITA, Kensuke YOSHIGA, Fumito KITANAKA, Masafumi TAKANO
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Publication number: 20240116408Abstract: A vehicle seat includes a hinge cover and a reclining lever. The hinge cover is disposed at a side portion of a seat cushion, and has an opening through which a recliner shaft of a recliner provided between the seat cushion and a seat back passes. The reclining lever is disposed at an outer side in a seat width direction with respect to the hinge cover, is rotatable about the recliner shaft to unlock the recliner, and has a protrusion protruding inward in the seat width direction, the protrusion facing an edge portion of the opening in a radial direction of the recliner shaft.Type: ApplicationFiled: October 6, 2023Publication date: April 11, 2024Inventors: Yukinori MIKITA, Kensuke YOSHIGA, Jun SHIRAI, Fumito KITANAKA, Masafumi TAKANO
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Patent number: 9368719Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.Type: GrantFiled: December 12, 2014Date of Patent: June 14, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
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Publication number: 20150171318Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layerType: ApplicationFiled: December 12, 2014Publication date: June 18, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
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Patent number: 8941088Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.Type: GrantFiled: September 27, 2013Date of Patent: January 27, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
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Patent number: 8829593Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.Type: GrantFiled: March 18, 2010Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Kensuke Takano, Masaaki Higuchi, Tetsuya Kai, Yoshio Ozawa
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Publication number: 20140021430Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layerType: ApplicationFiled: September 27, 2013Publication date: January 23, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
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Patent number: 8569728Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.Type: GrantFiled: March 22, 2010Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
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Patent number: 8530876Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.Type: GrantFiled: September 17, 2010Date of Patent: September 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa
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Patent number: 8450715Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide.Type: GrantFiled: September 16, 2010Date of Patent: May 28, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa, Ryota Fujitsuka, Mitsuru Sato
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Patent number: 8253189Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.Type: GrantFiled: July 28, 2009Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
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Publication number: 20120186604Abstract: According to one embodiment, a cleaning gas is sealed in a chamber of a semiconductor manufacturing apparatus, and the cleaning gas and deposits adhered in the chamber are reacted with each other to generate a reactive gas. After a predetermined time, the gas is exhausted from the chamber. Then, the chamber is evacuated while the cleaning gas is introduced into the chamber, and the reactive gas concentration contained in an exhausted gas is measured. The reactive gas concentration is compared with a determination value obtained when the deposits are removed from the chamber to determine whether the cleaning is terminated.Type: ApplicationFiled: September 15, 2011Publication date: July 26, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kensuke Takano, Shinji Miyazaki, Ken Ishii, Takashi Nakao
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Patent number: 8089121Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.Type: GrantFiled: September 22, 2009Date of Patent: January 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Masaru Kito
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Publication number: 20110193050Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a lower electrode, a variable resistance film, and an upper electrode. The lower electrode is on the substrate. The variable resistance film is on the lower electrode and stores data. The upper electrode is on the variable resistance film. The variable resistance film comprises a first film, and a second film. The first film is on a side of at least one of the upper electrode and the lower electrode and contains a metal. The second film is between the first film and the other electrode and contains the metal and oxygen. A composition ratio [O]/[Me] of oxygen to the metal in the second film is lower than a stoichiometric ratio and higher than the composition ratio [O]/[Me] in the first film. The composition ratio [0]/[Me] changes between the first film and the second film.Type: ApplicationFiled: September 17, 2010Publication date: August 11, 2011Inventors: Kensuke Takano, Katsuyuki Sekine, Yoshio Ozawa
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Publication number: 20110068316Abstract: According to one embodiment, a nonvolatile memory device includes a plurality of nonvolatile memory elements each of that includes a resistance change film. The resistance change film is capable of recording information by transitioning between a plurality of states having different resistances in response to at least one of a voltage applied to the resistance change film or a current passed through the resistance change film, and the resistance change film includes an oxide containing at least one element selected from the group consisting of Hf, Zr, Ni, Ta, W, Co, Al, Fe, Mn, Cr, and Nb. An impurity element contained in the resistance change film is at least one element selected from the group consisting of Mg, Ca, Sr, Ba, Sc, Y, La, V, Ta, B, Ga, In, Tl, C, Si, Ge, Sn, Pb, N, P, As, Sb, Bi, S, Se, and Te, and the impurity element has an absolute value of standard Gibbs energy of oxide formation larger than an absolute value of standard Gibbs energy of oxide formation of the element contained in the oxide.Type: ApplicationFiled: September 16, 2010Publication date: March 24, 2011Inventors: Kensuke TAKANO, Katsuyuki Sekine, Yoshio Ozawa, Ryota Fujitsuka, Mitsuru Sato
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Publication number: 20100314602Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layerType: ApplicationFiled: March 22, 2010Publication date: December 16, 2010Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
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Publication number: 20100237402Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.Type: ApplicationFiled: March 18, 2010Publication date: September 23, 2010Inventors: Katsuyuki SEKINE, Kensuke TAKANO, Masaaki HIGUCHI, Tetsuya KAI, Yoshio OZAWA
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Publication number: 20100123180Abstract: A nonvolatile semiconductor memory device includes a semiconductor layer as a channel, a conductive layer which is formed on a surface of the semiconductor layer with a first insulating layer and a second insulating layer interposed therebetween and functions as a control gate electrode; and a plurality of first charge storage layers formed between the first insulating layer and the second insulating layer. The plurality of first charge storage layers are formed in isolation from one another along a surface of the first insulating layer. The first insulating layer is formed so as to protrude towards the semiconductor layer at a position where each of the first charge storage layers is formed.Type: ApplicationFiled: September 22, 2009Publication date: May 20, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kensuke TAKANO, Yoshio Ozawa, Katsuyuki Sekine, Masaru Kito
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Publication number: 20100019312Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on a surface of the semiconductor region, a charge-storage insulating film formed on a surface of the tunnel insulating film and containing silicon and nitrogen, a block insulating film formed on a surface of the charge-storage insulating film, and a control gate electrode formed on a surface of the block insulating film, wherein the tunnel insulating film has a first insulating film formed on the surface of the semiconductor region and containing silicon and oxygen, a second insulating film formed on a surface of the first insulating film, and a third insulating film formed on a surface of the second insulating film and containing silicon and oxygen, and a charge trap state in the second insulating film has a lower density than that in the charge-storage insulating film.Type: ApplicationFiled: July 28, 2009Publication date: January 28, 2010Inventors: Katsuyuki SEKINE, Akiko Sekihara, Kensuke Takano, Yoshio Ozawa
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Patent number: 7615500Abstract: A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.Type: GrantFiled: March 9, 2007Date of Patent: November 10, 2009Assignees: NEC Electronics Corporation, NEC CorporationInventors: Kensuke Takano, Ichiro Yamamoto, Koji Watanabe