Patents by Inventor Kensuke Takenaka

Kensuke Takenaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240239816
    Abstract: Provided are new compounds that can have the property of being specifically taken up into cancer cells. In the present invention, novel 4-borono-phenylalanine derivatives, borono-phenylalanine derivatives having a heterocyclic skeleton, borono-phenylalanine derivatives having a fused ring structure, or pharmaceutically acceptable salts thereof are prepared. These compounds have the property of being taken up specifically by LAT1 and thus easily taken up specifically by cancer cells in the evaluation of LAT1 and LAT2 selective uptake, and can be conveniently used for neutron capture therapy and the like. A typical example is a compound represented by the following formula (I) or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: April 20, 2022
    Publication date: July 18, 2024
    Inventors: Yusuke MURATA, Hiroshi TAKENAKA, Yoichiro OHTA, Aya SUDANI, Miki ISHIMURA, Kensuke SUZUKI, Hiroyuki KAI
  • Publication number: 20240234496
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide semiconductor substrate of a first conductivity type; forming a first semiconductor layer of a first conductivity type at a surface of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface facing the silicon carbide semiconductor substrate; implanting ions of an inert element into a region of a surface layer of the first semiconductor layer, thereby, inducing ion implantation damage to a crystal structure of the region in which a long tail occurs, the surface layer being at the first surface of the first semiconductor layer; and implanting a dopant of a second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged, thereby, forming column regions of the second conductivity type.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 11, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kensuke TAKENAKA, Shinsuke HARADA
  • Publication number: 20240204051
    Abstract: A silicon carbide semiconductor substrate has a silicon carbide semiconductor substrate of a first conductivity type and a first semiconductor layer of the first conductivity type, provided at a front surface of the silicon carbide semiconductor substrate and having a doping concentration lower than that of the silicon carbide semiconductor substrate. A portion of the first semiconductor layer contains a dopant of a second conductivity type. A concentration of the dopant of the second conductivity type in the first semiconductor layer differs in a direction parallel to an orientation flat or in a direction orthogonal to the orientation flat, the orientation flat indicating a crystal axis direction, such that a distribution of a net doping concentration in the first semiconductor layer has a variation equal to or less than a predetermined threshold.
    Type: Application
    Filed: October 30, 2023
    Publication date: June 20, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kensuke TAKENAKA, Takeshi TAWARA, Shinsuke HARADA
  • Publication number: 20220285489
    Abstract: A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 8, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kensuke TAKENAKA, Takeshi TAWARA, Shinsuke HARADA
  • Publication number: 20220123112
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 21, 2022
    Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi TAWARA, Tomonori MIZUSHIMA, Shinichiro MATSUNAGA, Kensuke TAKENAKA, Manabu TAKEI, Hidekazu TSUCHIDA, Kouichi MURATA, Akihiro KOYAMA, Koji NAKAYAMA, Mitsuru SOMETANI, Yoshiyuki YONEZAWA, Yuji KIUCHI
  • Patent number: 10119920
    Abstract: There is provided a method that makes it possible to observe fine crystal defects using light of a visible region. The method includes illuminating a substrate with polarized parallel light and evaluating a crystal quality of at least a part of the substrate from an image obtained by light transmitted through or reflected by the substrate. The half width HW, the divergence angle DA, and the center wavelength CWL of the parallel light satisfy conditions given below 3?HW?100 0.1?DA?5 250?CWL?1600 where the center wavelength CWL and the half width HW are expressed in units of nm and the divergence angle DA is expressed in units of mrad.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: November 6, 2018
    Assignees: Fuji Electric Co., Ltd., Mipox Corporation
    Inventors: Seiji Mizutani, Kenji Nakagawa, Tomohisa Kato, Kensuke Takenaka
  • Publication number: 20180195952
    Abstract: There is provided a method that makes it possible to observe fine crystal defects using light of a visible region. The method includes illuminating a substrate with polarized parallel light and evaluating a crystal quality of at least a part of the substrate from an image obtained by light transmitted through or reflected by the substrate. The half width HW, the divergence angle DA, and the center wavelength CWL of the parallel light satisfy conditions given below 3?HW?100 0.1?DA?5 250?CWL?1600 where the center wavelength CWL and the half width HW are expressed in units of nm and the divergence angle DA is expressed in units of mrad.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 12, 2018
    Inventors: Seiji Mizutani, Kenji Nakagawa, Tomohisa Kato, Kensuke Takenaka
  • Publication number: 20130000728
    Abstract: A photovoltaic cell includes a photoelectric conversion element (PCE) in which an i-type silicon layer formed of a microcrystalline silicon film is provided between an n-type silicon layer and a p-type silicon layer, and the n-type silicon layer or p-type silicon layer positioned on a substrate side is configured of an amorphous silicon film. The PCE is formed wherein a mixture of a silane containing gas and hydrogen gas is introduced into a chamber and a seed layer formed of a microcrystalline silicon film is formed between the n-type silicon layer or p-type silicon layer positioned on the substrate side and the i-type silicon layer. The crystallization rate of a portion in contact with the n-type silicon layer or p-type silicon layer positioned on the substrate side is lower than that of the i-type silicon layer, and the rate increases continuously, or gradually in two or more stages, toward the i-type silicon layer side, continuing to the i-type silicon layer.
    Type: Application
    Filed: September 8, 2010
    Publication date: January 3, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Kensuke Takenaka
  • Publication number: 20110247685
    Abstract: A thin-film solar cell can include a light-reflective metal electrode layer, a first transparent conductive layer, a semiconductor layer and a front transparent conductive layer. The metal electrode layer can be formed on a substrate and has an uneven structure. The first transparent conductive layer can contain an amorphous transparent conductive material. The thin-film solar cell further can have a second transparent conductive layer between the first transparent conductive layer and the semiconductor layer. The second transparent conductive layer can be made of a crystalline transparent conductive material. Due to the first transparent conductive layer made amorphous, the surface roughness of the metal electrode layer is reduced so that the semiconductor layer can be formed with a good film quality.
    Type: Application
    Filed: March 9, 2011
    Publication date: October 13, 2011
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Kensuke Takenaka