Abstract: A method of designing a semiconductor integrated circuit makes it possible to reduce the amount of manual routing of a power wire. After a VDD power wire for a circuit block and a VSS power wire for the circuit block have been routed, the number and positions of y-direction VDD power wires are determined from consideration of the positions thereof. A first y-direction VDD power wire among the y-direction VDD power wires is used without being in contact with edges of the VSS power wire for the circuit block, but it overlays the routing position thereof. For that reason, non-selection of that first y-direction VDD power wire is determined. The other y-direction VDD power wires are subsequently routed automatically.

Abstract: A method of designing a semiconductor integrated circuit that makes it possible to reduce the manual work during the layout of power wiring. A first encircling power wire for supplying power to circuitry within a first circuit block, such as a memory block, is placed within that block. A second encircling power wire for supplying power to a random logic circuit block is placed to have a complicated shape, in order to avoid crossing the first encircling power wire. Two edges of the second encircling power wire are placed within the first circuit block. These two edges form a bent portion. By using these two edges for a portion that has a complicated shape of the second encircling power wire, it becomes possible to automate the routing of the other four edges of the second encircling power wire.

Abstract: A method is provided for designing a semiconductor integrated circuit having a logic macro-cell (101), a circular power source wiring (120) disposed around the logic macro-cell (101) in a ring shape and a signal wiring (150) that traverses the circular power source and is led out from the logic macro-cell to an outside. The circular power source wiring (120) is formed from a first layer Al wiring having a priority wiring direction extending in a lateral direction and a second layer Al wiring having a priority wiring direction extending in a vertical direction.

Abstract: Four gate electrodes of an n-type basic cell of a gate array are essentially oriented in a circular tangential direction of a radius relative to the center point Q of a cell. The electrodes have an upper and lower and a right and left symmetrical layout arrangement relative to the cell upper and lower center line and left and right center line. As a consequence, adjacent gate electrodes are positioned in a .+-.90.degree. rotating symmetry. Each gate electrode has wiring connection areas on both ends. The wiring connection areas overlap the pre-rotation wiring connection areas by a .+-.90.degree. rotation of the cell. Because the gate electrodes are essentially oriented along the circumference direction, the source and the drain are separated in the radial direction of the center of the cell. The wiring connection areas are not concentrated at the center of the cell, and this improves the wiring capabilities within the cell.