Abstract: The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

Abstract: A method for testing the memory in a system with two or more processing units is provided that generally involves the following acts. The memory is divided into two or more sections—one for each of the two or more processing units. Thus, each processing unit has an associated memory section. The memory is then checked with each memory section being checked with its associated processing unit. The act of checking the memory includes causing the address of a first encountered faulty location to be stored and causing a flag to be set in response to encountering a second faulty location. Finally, it is determined whether the flag has been set after the memory is checked. If so, a walk-through routine is then performed.

Abstract: The present invention provides for a method and system for allowing non-trusted partitions in large scale computer system to safely interrupt a processor without the risk of corruption or loss of interconnect bandwidth, and without the need for inefficient hardwiring. In operation code preferably located outside of the central processor, interrupts coming from outside the partition into specific addresses for determination of allowability into the partition.

Abstract: A method and apparatus are disclosed for allowing a system having multiple clock domains to be put into a known state to ensure repeatability during debugging tests. A global framing clock is created having a frequency equal to the lowest common denominator of all clocks in the system or to some divisor of thereof. At this frequency, the global framing clock ensures that it will have a rising edge at the same time that other clocks in the system have rising edges. The system clock and the global framing clock may be run throughout the system to integrated circuits. The global framing clock is used to control a system function, such as a reset or an interrupt function. When the system receives an asynchronous event, the global framing clock ensures that the event is not distributed to the system until the occurrence of a rising edge of the global framing clock.

Abstract: The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

Abstract: A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (“GFC”) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.

Abstract: A circuit for reconfiguring data into the particular data format for processors and system memory when operating in a particular dual-data format processing environment. The circuit uses an interface having read and write multiplexers to swap data bytes automatically, transforming data between big and little endian formats, based upon a control signal.

Abstract: A method and apparatus are disclosed for allowing a system having multiple clock domains to be put into a known state to ensure repeatability during debugging tests. A global framing clock is created having a frequency equal to the lowest common denominator of all clocks in the system or to some divisor of thereof. At this frequency, the global framing clock ensures that it will have a rising edge at the same time that other clocks in the system have rising edges. The system clock and the global framing clock may be run throughout the system to integrated circuits. The global framing clock is used to control a system function, such as a reset or an interrupt function. When the system receives an asynchronous event, the global framing clock ensures that the event is not distributed to the system until the occurrence of a rising edge of the global framing clock.

Abstract: A system and method for protecting memory space in a target storage device during a write operation in a computer system, comprising creating a single data packet, including user data that is to be written to said target storage device and key data that is used to establish authorization to store said user data; transmitting said single data packet to the target storage device; determining whether said key data is valid; writing said user data into said target storage device only when said key data is valid.

Abstract: A system and method for protecting memory space in a target storage device during a write operation in a computer system, comprising creating a single data packet, including user data that is to be written to said target storage device and key data that is used to establish authorization to store said user data; transmitting said single data packet to the target storage device; determining whether said key data is valid; writing said user data into said target storage device only when said key data is valid.

Abstract: The present invention provides for a method and system for ensuring error containment in packet based systems which are capable of large scaleability. In operation, an error bit travels with each data packet and if the bit is set, any device which receives the data packet acts to contain that packet. Thus, the error message travels only as far as the error data and does not stop processing at locations not affected by the error. Any system resource, upon receipt of a set error bit, must act to correct the fault.

Abstract: An I/O mapping within a system memory of a computing system assigns a fixed address to each I/O device and I/O bridge in a larger address region of the system than the number of address bits of the I/O devices and/or the I/O bridges would allow. This fixed address assignment eliminates problems associated with fragmentation of I/O memory space of a conventional variable address assignment when I/O devices and/or I/O bridges are replaced on-line, i.e., hot-swapped. The I/O mapping utilizes a greater number of address bits than the address bits available from I/O devices to assign a much larger address space to each device by translating the larger number of bits address from the system to the smaller number of bits address of the I/O devices.

Abstract: A system and method for protecting memory space in a target storage device during a write operation in a computer system, comprising creating a single data packet, including user data that is to be written to said target storage device and key data that is used to establish authorization to store said user data; transmitting said single data packet to the target storage device; determining whether said key data is valid; writing said user data into said target storage device only when said key data is valid.

Abstract: A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into memory segments, memory segments of equal size from different memories arranged or organized into interleave groups. An initial largest interleave group is selected and a corresponding first interleave entry is generated in a table. The interleave entry maps a corresponding initial logical address space into each of the memory segments corresponding to the first interleave group. A total memory size included thus far in the table is calculated and successive next larger groups that are integer divisors of the total memory, i.e., the partial sums formed by groups selected thus far. These steps are repeated until all of the contiguous logical address space has been mapped onto the memories.

Abstract: A system and method is described in which protected memory writes are achieved in single transaction without leaving open a window in time for erroneous data to corrupt space in a target register. A single data packet preferably includes both user data to be written to a target storage device or location as well as the key data for authorizing the writing of such user data. Key data is preferably calculated by manipulating user data contained in the same packet or transmission thereby simplifying a verification process conducted the controller associated with target storage location.

Abstract: A processor-to-memory interface (PMI) for a multiprocessor computer system and a computer testing method are disclosed. The multi-processor computer system provides a processor-to-memory-bus interface for each microprocessor. Each processor-to-memory-bus interface translates between microprocessor and bus protocols and manages respective level-2 (L2) caches. In addition, each interface includes test-event hardware that, when enabled causes test events to be generated with a predetermined repetition rate. The test events are selected for having a non-zero probability of causing system events that are complex, rare and non-fatal. These include assertions of "busy" and "wait" conditions and corrections of single-bit cache errors. The test-event hardware includes a timing generator that determines when test events are to be generated, an event-flag register that determines which events are to be generated, and a test-event generator that generates test-events at the times determined by the timing generator.