Abstract: Methods are disclosed. A method may include a method of generating an integrated circuit design. The method of generating an integrated circuit design may include generating a contextual cell including a super-master and defining at least one sub-master, the at least one sub-master derived from parameterized values and a context of an instance of the super-master.

Abstract: Methods for generating a cell set for an analog design tool are disclosed. A method comprises receiving, at a cell generator, one or more electronic files of a process-specific architectural cell (AP_Cell) having wiring for power and ground, FILL, wherein the AP_Cell is configured according to a first manufacturing process. The method further includes receiving, at the cell generator, one or more electronic files of a schematic cell (S_Cell) having internal wiring between circuit elements to provide a function for the S_Cell. The method also includes merging data from the one or more electronic files of the AP_Cell and the one or more electronic files of the S_Cell to generate a process-specific schematic cell (SP_Cell) used as a building block for a physical layout of an analog IC, wherein the process-specific schematic cell comprises one or more electronic files. Related devices are also described herein.

Abstract: A method for designing a semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by an analog circuit designer using an analog design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.

Abstract: Methods for generating a cell set for an analog design tool are disclosed. A method comprises receiving, at a cell generator, one or more electronic files of a process-specific architectural cell (AP_Cell) having wiring for power and ground, FILL, wherein the AP_Cell is configured according to a first manufacturing process. The method further includes receiving, at the cell generator, one or more electronic files of a schematic cell (S_Cell) having internal wiring between circuit elements to provide a function for the S_Cell. The method also includes merging data from the one or more electronic files of the AP_Cell and the one or more electronic files of the S_Cell to generate a process-specific schematic cell (SP_Cell) used as a building block for a physical layout of an analog IC, wherein the process-specific schematic cell comprises one or more electronic files. Related devices are also described herein.

Abstract: A method for designing an semiconductor integrated circuit is disclosed, including generating a physical layout from a schematic layout of the analog integrated circuit. The method comprises retrieving, with a processor, pre-defined cells having physical layout information for a specific process stored in a memory device responsive to the schematic layout being created by a circuit designer using an analog circuit design tool, building the physical layout by connecting the retrieved pre-defined cells according to the schematic layout, and storing the physical layout in the memory device. Related systems and computer-readable media are also described herein.

Abstract: A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit.

Abstract: A pipelined current mode analog-to-digital converter, including: a plurality of stages each having a first sample and hold circuit configured to receive an analog signal having a current; the sample and hold circuit having at least first and second outputs; the first output having a current from a current copier configured to copy the analog signal; the second output having a current from a current mirror configured to mirror the analog signal; a current mode analog-to-digital converter configured to create a digital signal from the second output, the second output being connected to an input of the analog-to-digital converter; and a current mode digital-to-analog converter configured to convert the digital signal back to an analog signal, wherein an output of the digital-to-analog converter is subtracted from the first output of the sample and hold circuit.

Abstract: A current steering folding circuit is provided. The current steering folding circuit includes a load and at least one current source for drawing a current from the load. The current steering folding circuit also includes a first output signal terminal for providing a first output signal, and a second output signal terminal for providing a second output signal. A current steering section is also provided. The current steering section steers the current between the first output signal terminal and the second output signal terminal based on an input signal. The first output signal is substantially equal to the second output signal for N values of the input signal. Advantageously, the number of current sources does not exceed N.

Abstract: A current steering folding circuit is provided. The current steering folding circuit includes a load and at least one current source for drawing a current from the load. The current steering folding circuit also includes a first output signal terminal for providing a first output signal, and a second output signal terminal for providing a second output signal. A current steering section is also provided. The current steering section steers the current between the first output signal terminal and the second output signal terminal based on an input signal. The first output signal is substantially equal to the second output signal for N values of the input signal. Advantageously, the number of current sources does not exceed N.

Abstract: A logical circuit array is provided in which the AND and OR planes are folded together and all of the logic cell transistor gates are oriented in the same direction. The array comprises a plurality of AND rows R.sub.0 through R.sub.n, and means for precharging the AND rows to one logic level, e.g. V.sub.DD. An additional row R.sub.a is provided along with means for precharging the additional row to another logic level, e.g., ground. The array includes a plurality of data columns and an output column coupled to AND row R.sub.0. A plurality of logic cells is divided among AND rows R.sub.0 through R.sub.n-1. Each of the logic cells has an input terminal coupled to a data column, a first output terminal connected to the AND row with which the logic cell is associated, and a second output terminal connected to the next successive AND row in the array. A plurality of logic cells is associated with AND row R.sub.

Abstract: A clocked storage logic array is formed from a plurality of columns and a plurality of rows disposed orthogonal to the columns. Logic cells interconnect selected columns and rows. Storage cells are operatively associated with some of the columns in the array, known as data columns. The storage cells utilize only two column conductors which are time shared to provide a data path from a memory element in the storage cell to a specified row or rows and back from the row(s) through the same column conductors to the memory. A plurality of phase-displaced clock periods are generated which operate in association with the storage cells to enable the two column conductors to be time shared. The clock periods also cooperate with logic cells to cause selected rows to assume binary states determined by the binary state of interconnected columns, and vice-versa.

Abstract: A clocked structured logic array functions in a dynamic, rather than static, mode of operation. The column output conductors and row conductors of the array are precharged to a predetermined voltage level at the beginning of a clock cycle. At the termination of a first phase of the clock cycle, the column conductors are selectively discharged in accordance with information stored in column memory elements. Upon termination of a second phase of the clock cycle, the row conductors are selectively discharged in accordance with a predetermined program, and responsive to the states of the column output conductors. The states of the row conductors are selectively transmitted to the column input conductors, and during a third phase of the clock cycle the information related to the states of the input conductors is transmitted to the memory elements.

Abstract: A clocked storage logic array is formed from a plurality of columns and a plurality of rows disposed orthogonal to the columns. Logic cells interconnect selected columns and rows. At least one storage cell is operatively associated with at least one data column. The storage cell utilizes only two column conductors which are time shared to provide a data path from a memory element in the storage cell to a specified row or rows and back from the row(s) through the same column conductors to the memory. A plurality of phase-displaced clock periods are generated which operate in association with logic cells to cause selected rows to assume binary states determined by the binary state of interconnected columns, and vice-versa. The clock periods also cooperate with storage cells to enable the two column conductors to be time shared.

Abstract: An I.sup.2 L circuit is provided for sensing relatively small differences in magnitude between two input signals. A dual input bistable circuit generates an output representative of the degree to which each of the bistable circuit inputs is actuated, subsequent to the energization of the bistable circuit by a current source in the form of an injector transistor, which is disabled to reset the bistable circuit. A pair of load transistors are provided, the control terminals of which are, respectively, connected to receive the input signals. Each load transistor serves to actuate a different one of the bistable means inputs to a degree dependent upon the conductivity thereof, which, in turn, is dependent upon the magnitude of the input signal connected thereto. The load transistors also serve to isolate the source of the input signals from the energizing injector current, to prevent the sensing circuit from disrupting the state of the source of the input signals.

Abstract: The memory unit comprises a plurality of bipolar inverter transistors and an equal number of injector transistors, each of which acts as a current source for a different one of the inverter transistors. Means are provided for cross-coupling a first and a second of the inverter transistors to form a flip-flop. Third, fourth and fifth inverter transistors provide input data flow from the data line to the cross-coupled first and second inverters, in accordance with a write control sixth inverter transistor connected to receive a write signal. A seventh inverter transistor provides data output flow between the cross-coupled first and second inverter transistors and the data line in accordance with the read control eighth inverter transistor connected to receive a read signal.