Patents by Inventor Kent Hwang
Kent Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7180886Abstract: In a synchronized data communication on a one-wired bus, it transmits and receives a synchronizing signal that segments part of or all proportions of the data signal by use of three electrically distinguishable statuses for the identifier of the synchronizing signal and the logic states of the data signal to increase the endurance of frequency displacement and resist influences of the interference of external conditions, low quality of transmission medium, and limitation of transmission distance and make the reliability and correctness of the signal transmission improve substantially. It is also clearly illustrated the feasibility and simplicity for implementing the one-wired synchronized communication by a plurality of exemplary signal types and a transceiver circuitry.Type: GrantFiled: May 24, 2002Date of Patent: February 20, 2007Assignee: Richtek Technology Corp.Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
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Patent number: 6969980Abstract: A pulse width modulator includes an amplifier module, a comparator module, and a filter module. The amplifier module receives a feedback voltage signal from a passive network, and generates first and second non-inverted voltage signals and first and second inverted voltage signals in response to the feedback voltage signal. The comparator module receives the first and second non-inverted voltage signals and the first and second inverted voltage signals, and provides first and second differential voltage signals corresponding to the first and second non-inverted voltage signals and the first and second inverted voltage signals. The filter module is coupled between the amplifier module and the comparator module, and is operable so as to attenuate high frequency components of the first and second non-inverted voltage signals. As such, the presence of noise in the feedback voltage signal does not affect differential operation of the comparator module.Type: GrantFiled: May 21, 2004Date of Patent: November 29, 2005Assignee: Richtek Technology Corp.Inventors: Liang-Pin Tai, Kent Hwang, Jian-Rong Huang, Kuo-Ping Liu, Cheng-Hsuan Fan, Ko-Cheng Wang, Yu-Fan Liao
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Publication number: 20050258813Abstract: A pulse width modulator includes an amplifier module, a comparator module, and a filter module. The amplifier module receives a feedback voltage signal from a passive network, and generates first and second non-inverted voltage signals and first and second inverted voltage signals in response to the feedback voltage signal. The comparator module receives the first and second non-inverted voltage signals and the first and second inverted voltage signals, and provides first and second differential voltage signals corresponding to the first and second non-inverted voltage signals and the first and second inverted voltage signals. The filter module is coupled between the amplifier module and the comparator module, and is operable so as to attenuate high frequency components of the first and second non-inverted voltage signals. As such, the presence of noise in the feedback voltage signal does not affect differential operation of the comparator module.Type: ApplicationFiled: May 21, 2004Publication date: November 24, 2005Inventors: Liang-Pin Tai, Kent Hwang, Jian-Rong Huang, Kuo-Ping Liu, Cheng-Hsuan Fan, Ko-Cheng Wang, Yu-Fan Liao
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Patent number: 6844709Abstract: A programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current is provided to monitor a supply voltage, by which only one programming pin can configure three voltage levels for the threshold voltage to be compared to the supply voltage. The programming pin is connected with a voltage select signal that is defined to be high, low or floating states each determines a setting voltage among three levels corresponding to the three threshold voltages, respectively, by a voltage select circuit. A sample/hold circuit in combination with a switch arrangement is further connected to the voltage select circuit such that the programmable voltage supervisory circuit is only operationable during the duty of a clock and thereby to reduce the power consumption thereof by squeezing the duty.Type: GrantFiled: October 30, 2002Date of Patent: January 18, 2005Assignee: Richtek Technology, Corp.Inventors: Chao-Hsuan Chuang, Jing-Meng Liu, Cheng-Hsuan Fan, Kent Hwang
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Patent number: 6809616Abstract: An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source.Type: GrantFiled: January 15, 2003Date of Patent: October 26, 2004Assignee: Richtex Technology Corp.Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
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Patent number: 6747508Abstract: A resistance adjustable of resistance mirror circuit having a master resistor R0, a reference current source terminal providing a current value I0 through the master resistor R0 to ground; a first transistor; a current mirror source terminal providing a current value n I0, through the first transistor to ground; an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R0, and an output terminal connecting to a gate of the first transistor; a mirror resistor set composed of a plurality of transistors in parallel each other and having their source electrode connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers.Type: GrantFiled: August 28, 2002Date of Patent: June 8, 2004Assignee: Richtek Technology Corp.Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
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Publication number: 20040085053Abstract: A programmable voltage supervisory circuit and method with minimum programming pins and low quiescent current is provided to monitor a supply voltage, by which only one programming pin can configure three voltage levels for the threshold voltage to be compared to the supply voltage. The programming pin is connected with a voltage select signal that is defined to be high, low or floating states each determines a setting voltage among three levels corresponding to the three threshold voltages, respectively, by a voltage select circuit. A sample/hold circuit in combination with a switch arrangement is further connected to the voltage select circuit such that the programmable voltage supervisory circuit is only operationable during the duty of a clock and thereby to reduce the power consumption thereof by squeezing the duty.Type: ApplicationFiled: October 30, 2002Publication date: May 6, 2004Inventors: Chao-Hsuan Chuang, Jing-Meng Liu, Cheng-Hsuan Fan, Kent Hwang
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Publication number: 20040008096Abstract: An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source.Type: ApplicationFiled: January 15, 2003Publication date: January 15, 2004Applicant: RichTek Technology Corp.Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
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Publication number: 20030219004Abstract: In a synchronized data communication on a one-wired bus, it transmits and receives a synchronizing signal that segments part of or all proportions of the data signal by use of three electrically distinguishable statuses for the identifier of the synchronizing signal and the logic states of the data signal to increase the endurance of frequency displacement and resist influences of the interference of external conditions, low quality of transmission medium, and limitation of transmission distance and make the reliability and correctness of the signal transmission improve substantially. It is also clearly illustrated the feasibility and simplicity for implementing the one-wired synchronized communication by a plurality of exemplary signal types and a transceiver circuitry.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
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Publication number: 20030141923Abstract: A resistance adjustable of resistance mirror circuit comprises: a master resistor R0, a reference current source terminal providing a current value I0 through the master resistor R0 to ground; a first transistor; a current mirror source terminal providing a current value nI0, through the first transistor to ground; an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R0, and an output terminal connecting to a gate of the first transistor; a mirror resistor set composed of a plurality of transistors in parallel each other and having their source electrode connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers.Type: ApplicationFiled: August 28, 2002Publication date: July 31, 2003Applicant: Richtek Technology Corp.Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan