Patents by Inventor Kent Jaeger
Kent Jaeger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240080019Abstract: A device includes a temperature-variable voltage controller, in which the temperature-variable voltage controller comprises: a voltage regulator; a process monitor circuit coupled to the voltage regulator, in which the process monitor circuit includes a ring oscillator, and a frequency counter coupled to an output of the ring oscillator; and a temperature-variable current source coupled to the voltage regulator so that, during operation, the output voltage of the voltage regulator is compensated based on a change in temperature of the temperature-variable current source.Type: ApplicationFiled: November 10, 2023Publication date: March 7, 2024Applicant: Huawei Technologies Co., Ltd.Inventors: Kent Jaeger, Lawrence E. Connell, Neal Hollenbeck
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Patent number: 11595003Abstract: The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.Type: GrantFiled: November 5, 2020Date of Patent: February 28, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Lawrence E. Connell, Kent Jaeger
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Patent number: 11569393Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: GrantFiled: March 9, 2020Date of Patent: January 31, 2023Assignee: Futurewei Technologies, Inc.Inventors: Brian Creed, Lawrence E. Connell, Kent Jaeger, Matthew Richard Miller
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Publication number: 20210099131Abstract: The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.Type: ApplicationFiled: November 5, 2020Publication date: April 1, 2021Applicant: Huawei Technologies Co., Ltd.Inventors: Lawrence E. Connell, Kent Jaeger
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Publication number: 20200321479Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: ApplicationFiled: March 9, 2020Publication date: October 8, 2020Applicant: Futurewei Technologies, Inc.Inventors: Brian Creed, Lawrence E. Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 10586878Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: GrantFiled: December 4, 2017Date of Patent: March 10, 2020Assignee: Futurewei Technologies, Inc.Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 10404212Abstract: The disclosure relates to technology for shifting a frequency range of a signal. In one aspect, a circuit comprises a frequency mixer, a frequency synthesizer configured to generate an oscillator signal, a programmable driver, and a controller. The programmable driver is configured to receive the oscillator signal from the frequency synthesizer and to provide the oscillator signal to the oscillator input of the frequency mixer. The programmable driver is configured to have a variable drive strength. The controller is configured to control the drive strength of the programmable driver based on a frequency of the oscillator signal to adjust a rise time and a fall time of the oscillator signal at the oscillator input of the frequency mixer.Type: GrantFiled: August 6, 2018Date of Patent: September 3, 2019Assignee: Futurewei Technologies, Inc.Inventors: Lawrence E. Connell, Kent Jaeger
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Publication number: 20180090627Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: ApplicationFiled: December 4, 2017Publication date: March 29, 2018Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 9837555Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: GrantFiled: April 15, 2015Date of Patent: December 5, 2017Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 9768165Abstract: An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.Type: GrantFiled: September 2, 2016Date of Patent: September 19, 2017Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Kent Jaeger, Lawrence Connell
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Patent number: 9647622Abstract: An embodiment method includes measuring, by a calibration device, a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting and measuring, by a calibration device, a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting. The method further includes calculating, by the calibration device, an offset voltage of a signal path including the VGA using the first output voltage and the second output voltage and calculating, by the calibration device, an internal offset voltage of the VGA using the first output voltage and the second output voltage.Type: GrantFiled: October 22, 2015Date of Patent: May 9, 2017Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Kent Jaeger, Zhihang Zhang, Matthew Miller, Ramesh Chadalawada
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Publication number: 20170117861Abstract: An embodiment method includes measuring, by a calibration device, a first output voltage of a variable gain amplifier (VGA) when the VGA is set at a first gain setting and measuring, by a calibration device, a second output voltage of the VGA when the VGA is set at a second gain setting different from the first gain setting. The method further includes calculating, by the calibration device, an offset voltage of a signal path including the VGA using the first output voltage and the second output voltage and calculating, by the calibration device, an internal offset voltage of the VGA using the first output voltage and the second output voltage.Type: ApplicationFiled: October 22, 2015Publication date: April 27, 2017Inventors: Kent Jaeger, Zhihang Zhang, Matthew Miller, Ramesh Chadalawada
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Publication number: 20160372464Abstract: An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Kent Jaeger, Lawrence Connell
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Publication number: 20160308073Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.Type: ApplicationFiled: April 15, 2015Publication date: October 20, 2016Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
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Patent number: 9449969Abstract: An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.Type: GrantFiled: June 3, 2015Date of Patent: September 20, 2016Assignee: FUTUREWEI TECHNOLOGIES, INC.Inventors: Kent Jaeger, Lawrence E. Connell
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Patent number: 9166571Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.Type: GrantFiled: July 3, 2013Date of Patent: October 20, 2015Assignee: Futurewei Technologies, Inc.Inventors: Lawrence E. Connell, Daniel P. McCarthy, Brian T. Creed, Kent Jaeger
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Patent number: 8928369Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.Type: GrantFiled: July 31, 2013Date of Patent: January 6, 2015Assignee: Futurewei Technologies, Inc.Inventors: Kent Jaeger, Lawrence E. Connell, Daniel P. McCarthy, Brian T. Creed
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Publication number: 20140361814Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal.Type: ApplicationFiled: June 11, 2013Publication date: December 11, 2014Inventors: Lawrence E. Connell, Brian T. Creed, Daniel P. McCarthy, Kent Jaeger
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Publication number: 20140361821Abstract: An apparatus comprising a latch comprising a differential inverter configured to receive a differential input signal and generate a differential output signal, a pair of cross-coupled inverters coupled to the differential inverter, and a first clock switch configured to couple the differential inverter to a voltage source, a second clock switch configured to couple the differential inverter to a ground, wherein the first clock switch and the second clock switch are configured to receive a differential clock signal, and wherein the first clock switch and the second clock switch are both open or both closed depending on the differential clock signal, a second latch, wherein the first latch and the second latch are configured as a frequency divider, and a logic circuit coupled to each latch, wherein the logic circuits are configured to generate both an in-phase reference output signal and a quadrature output signal.Type: ApplicationFiled: July 3, 2013Publication date: December 11, 2014Inventors: Lawrence E. Connell, Daniel P. McCarthy, Brian T. Creed, Kent Jaeger
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Patent number: 7733181Abstract: Methods and corresponding systems for amplifying an input signal include inputting first and second differential input signals into first and second circuit legs, respectively, wherein the first circuit leg includes a first transistor coupled in series with a first variable current source, and wherein the second circuit leg includes a second transistor coupled in series with a second variable current source. The first and second variable current sources are dynamically set to provide first and second bias currents in response to the first and second differential input signals, wherein the first bias current is set inversely proportional to the second bias current. The first and second bias currents are sunk in the first and second circuit legs, respectively. First and second differential output signals are output from the first and second circuit legs, respectively.Type: GrantFiled: May 23, 2008Date of Patent: June 8, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Kent Jaeger, Lawrence E. Connell