Abstract: A computer implemented method converts a data set of a first type to a data set type of a second type. The method includes casting up a first data set of a first type to a prescribed data set type that is large enough to encompass a data set of a second type. The method then includes casting down the casted up first data set from the prescribed data set type to the second data set of the second data set type.

Abstract: A behavioral synthesis process is provided that transforms a generalized behavioral design into a detailed interconnection of design objects to implement the behavior. A design database including design objects is generated as a user creates a diagrammatic representation of a desired behavior using a user interface. The synthesis process, which includes multiple concurrent threads, transforms the design objects. The transformation of the design objects can be achieved by propagating information from a particular design object to another design object. As the concurrent threads operate, the design objects are incrementally transformed according to objectives of an overall design.

Abstract: A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem, a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.

Abstract: A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem, a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.

Abstract: A computer system comprising a first block which includes multiple processing subsystem, a second block which includes multiple processing subsystem, a third block which includes multiple processing subsystem , a fourth block which includes multiple processing subsystem, a first communication and processing subsystem that interconnects subsystem of the first and second blocks, a second communication and processing subsystem that interconnects subsystem of the third and fourth blocks, a third communication and processing subsystem that interconnects subsystem of the first and fourth blocks; and a fourth communication and processing subsystem that interconnects subsystem of the second and third blocks, wherein respective subsystem include a respective processing elements and a respective communication and processing unit interconnecting the respective processing elements.

Abstract: An integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dynamically reconfigured, the Reconfigurable Instruction Execution Unit can be dynamically changed to implement complex operations in hardware rather than in time-consuming software routines. This feature allows the computing device to operate at speeds that are orders of magnitude greater than traditional RISC or CISC counterparts. In addition, the programmability of the computing device makes it very flexible and hence, ideally suited to handle a large number of very complex and different applications.

Abstract: A fault tolerant IC device is made from a wafer of field programmable gate arrays (FGPA's). Each FGPA is first tested and a wafer map of defective FGPA locations is recorded. A hardware description defines desired circuit operation either via a schematic or a functional description such as a equation or a formula. The hardware description is compiled into a list of required wafer resources and a partitioner allocates this list among the resources available in the FGPA's on the wafer. A automatic router then interconnects to implement the circuit function using the wafer map to avoid all defective FGPA locations. A bit-stream generator then generates the configuration data to program each FGPA to perform it's desired function. The resulting wafer-scale circuit is wafer fault tolerant since the programming avoids and non-functional portions of the wafer. Possible embodiments include XILINX FGPAs, custom wafers with FGPAs and special circuitry and wafers having FGPAs programmed to form RISC processors.

Abstract: An integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dynamically reconfigured, the Reconfigurable Instruction Execution Unit can be dynamically changed to implement complex operations in hardware rather than in time-consuming software routines. This feature allows the computing device to operate at speeds that are orders of magnitude greater than traditional RISC or CISC counterparts. In addition, the programmability of the computing device makes it very flexible and hence, ideally suited to handle a large number of very complex and different applications.