Patents by Inventor Kent STALNAKER
Kent STALNAKER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10164633Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: GrantFiled: July 10, 2017Date of Patent: December 25, 2018Assignee: Invensas CorporationInventors: Curtis Dicke, George Courville, David Edward Fisch, Randall Sandusky, Kent Stalnaker
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Publication number: 20170310322Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Applicant: Invensas CorporationInventors: Curtis Dicke, George Courville, David Edward Fisch, Randall Sandusky, Kent Stalnaker
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Patent number: 9705497Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: GrantFiled: August 18, 2015Date of Patent: July 11, 2017Assignee: Invensas CorporationInventors: Curtis Dicke, George Courville, David Fisch, Randall Sandusky, Kent Stalnaker
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Patent number: 9548101Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: GrantFiled: March 9, 2016Date of Patent: January 17, 2017Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Publication number: 20160189765Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: ApplicationFiled: March 9, 2016Publication date: June 30, 2016Applicant: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Publication number: 20160094223Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: ApplicationFiled: August 18, 2015Publication date: March 31, 2016Inventors: Curtis DICKE, George COURVILLE, David FISCH, Randall SANDUSKY, Kent STALNAKER
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Patent number: 9299398Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: GrantFiled: April 10, 2015Date of Patent: March 29, 2016Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Patent number: 9111671Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: GrantFiled: May 23, 2013Date of Patent: August 18, 2015Assignee: INVENSAS CORPORATIONInventors: Curtis Dicke, George Courville, David Fisch, Randall Sandusky, Kent Stalnaker
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Publication number: 20150213847Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: ApplicationFiled: April 10, 2015Publication date: July 30, 2015Applicant: INVENSAS CORPORATIONInventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Patent number: 9007866Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.Type: GrantFiled: April 23, 2013Date of Patent: April 14, 2015Assignee: Tessera Inc.Inventors: David Edward Fisch, William C. Plants, Kent Stalnaker
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Publication number: 20140049356Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.Type: ApplicationFiled: May 23, 2013Publication date: February 20, 2014Inventors: Curtis DICKE, George COURVILLE, David FISCH, Randall SANDUSKY, Kent STALNAKER
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Patent number: 5671392Abstract: A circuit and method for a memory device, such as a synchronous dynamic random access memory (SDRAM) having at least two memory banks. Columns of at least two memory banks are concurrently addressable to permit data to be written to, or read from, the at least two memory banks concurrently. By writing data concurrently to more than one memory bank, testing of the memory of the memory device can be effectuated in a reduced period of time. Data can also be written or read from a single bank in a multi-bank RAM without requiring that a particular bank be specified during a read/write command.Type: GrantFiled: April 11, 1995Date of Patent: September 23, 1997Assignees: United Memories, Inc., Nippon Steel Semiconductor CorporationInventors: Michael Parris, H. Kent Stalnaker