Abstract: A switch connection lock and release mechanism is disclosed to prevent out-of-order frames from being received by FC and/or SATA devices. The mechanism includes a set of previous AL_PA registers, alpa_reg[N:0], one for each port, and a bit vector, prev_conn[M:0], one bit for each Buffer Bank (BB). If a connection is closed prematurely, the valid AL_PA of the destination device and the source port number are stored in the previous AL_PA register associated with the destination port, and the bit in the bit vector associated with the source BB is asserted. Together, the valid AL_PA, the source port and the asserted bit form a connection lock on the destination port that effectively will deny access to the destination port to all BBs with the same destination AL_PA and source port number except the source BB.

Abstract: A switch connection lock and release mechanism is disclosed to prevent out-of-order frames from being received by FC and/or SATA devices. The mechanism includes a set of previous AL_PA registers, alpa_reg[N: 0], one for each port, and a bit vector, prev_conn[M:0], one bit for each Buffer Bank (BB). If a connection is closed prematurely, the valid AL_PA of the destination device and the source port number are stored in the previous AL_PA register associated with the destination port, and the bit in the bit vector associated with the source BB is asserted. Together, the valid AL_PA, the source port and the asserted bit form a connection lock on the destination port that effectively will deny access to the destination port to all BBs with the same destination AL_PA and source port number except the source BB.