Patents by Inventor Kenta MATSUYAMA
Kenta MATSUYAMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11398574Abstract: A solar cell includes: a semiconductor substrate which includes a first principal surface and a second principal surface; a first semiconductor layer of the first conductivity type disposed above the first principal surface; and a second semiconductor layer of a second conductivity type disposed below the second principal surface. The semiconductor substrate includes: a first impurity region of the first conductivity type; a second impurity region of the first conductivity type disposed between the first impurity region and the first semiconductor layer; and a third impurity region of the first conductivity type disposed between the first impurity region and the second semiconductor layer. A concentration of an impurity in the second impurity region is higher than a concentration of the impurity in the third impurity region, and the concentration of the impurity in the third impurity region is higher than a concentration of the impurity in the first impurity region.Type: GrantFiled: March 25, 2020Date of Patent: July 26, 2022Assignee: PANASONIC HOLDINGS CORPORATIONInventors: Kazunori Fujita, Kenta Matsuyama
-
Patent number: 11056601Abstract: A solar cell includes an n-type silicon substrate having a first main surface and a second main surface, an n-type first semiconductor layer disposed above the first main surface, a first intrinsic semiconductor layer disposed between the first main surface and the first semiconductor layer, a p-type second semiconductor layer disposed on the second main surface, and a second intrinsic semiconductor layer disposed between the second main surface and the second semiconductor layer. An oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer is lower than an oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer. An oxygen concentration at an interface between the second intrinsic semiconductor layer and the second semiconductor layer is higher than an oxygen concentration at an interface between the first intrinsic semiconductor layer and the first semiconductor layer.Type: GrantFiled: September 10, 2019Date of Patent: July 6, 2021Assignee: PANASONIC CORPORATIONInventors: Taiki Hashiguchi, Kenta Matsuyama
-
Patent number: 10923610Abstract: Provided is a solar cell that can suppress loss of power generation performance of a solar cell module when shaded and a solar cell module having the solar cell. An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: GrantFiled: November 30, 2016Date of Patent: February 16, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
-
Patent number: 10872986Abstract: A solar cell is made which has a first conduction-type crystalline silicon substrate having a texture provided on the surface, and an i-type amorphous silicon layer located on the surface of the crystalline silicon substrate, wherein the texture has a larger radius of curvature R1 of root parts thereof than the radius of curvature R2 of peak parts thereof. The crystalline silicon substrate has a first conduction-type highly-doped region containing a first conduction-type dopant on the surface thereof, and the dopant concentration in the first conduction-type highly-doped region is higher than that in the center in the thickness direction of the crystalline silicon substrate.Type: GrantFiled: July 24, 2017Date of Patent: December 22, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Kenta Matsuyama
-
Publication number: 20200313009Abstract: A solar cell includes: a semiconductor substrate which includes a first principal surface and a second principal surface; a first semiconductor layer of the first conductivity type disposed above the first principal surface; and a second semiconductor layer of a second conductivity type disposed below the second principal surface. The semiconductor substrate includes: a first impurity region of the first conductivity type; a second impurity region of the first conductivity type disposed between the first impurity region and the first semiconductor layer; and a third impurity region of the first conductivity type disposed between the first impurity region and the second semiconductor layer. A concentration of an impurity in the second impurity region is higher than a concentration of the impurity in the third impurity region, and the concentration of the impurity in the third impurity region is higher than a concentration of the impurity in the first impurity region.Type: ApplicationFiled: March 25, 2020Publication date: October 1, 2020Inventors: Kazunori Fujita, Kenta Matsuyama
-
Patent number: 10784396Abstract: An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: GrantFiled: December 29, 2016Date of Patent: September 22, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
-
Publication number: 20200111928Abstract: A solar cell includes an n-type silicon substrate having a first main surface and a second main surface, an n-type first semiconductor layer disposed above the first main surface, a first intrinsic semiconductor layer disposed between the first main surface and the first semiconductor layer, a p-type second semiconductor layer disposed on the second main surface, and a second intrinsic semiconductor layer disposed between the second main surface and the second semiconductor layer. An oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer is lower than an oxygen concentration at an interface between the silicon substrate and the second intrinsic semiconductor layer. An oxygen concentration at an interface between the second intrinsic semiconductor layer and the second semiconductor layer is higher than an oxygen concentration at an interface between the first intrinsic semiconductor layer and the first semiconductor layer.Type: ApplicationFiled: September 10, 2019Publication date: April 9, 2020Inventors: Taiki HASHIGUCHI, Kenta MATSUYAMA
-
Publication number: 20190157489Abstract: A solar cell according to one embodiment of the present invention is provided with: an n-type crystalline silicon wafer having an n+ layer in the entire wafer surface and in the vicinity thereof, said n+ layer having a higher n-type dopant concentration than the other regions; a low concentration P-containing silicon oxide layer which is formed on a light receiving surface of the n-type crystalline silicon wafer; an n-type crystalline silicon layer which is formed on the low concentration P-containing silicon oxide layer; and a p-type amorphous silicon layer which is formed on the back surface side of the n-type crystalline silicon wafer.Type: ApplicationFiled: January 28, 2019Publication date: May 23, 2019Applicant: Panasonic Intellectual Property Management Co., Lt d.Inventors: Kenta Matsuyama, Kazunori Fujita, Satoru Shimada
-
Publication number: 20180040747Abstract: A solar cell is made which has a first conduction-type crystalline silicon substrate having a texture provided on the surface, and an i-type amorphous silicon layer located on the surface of the crystalline silicon substrate, wherein the texture has a larger radius of curvature R1 of root parts thereof than the radius of curvature R2 of peak parts thereof. The crystalline silicon substrate has a first conduction-type highly-doped region containing a first conduction-type dopant on the surface thereof, and the dopant concentration in the first conduction-type highly-doped region is higher than that in the center in the thickness direction of the crystalline silicon substrate.Type: ApplicationFiled: July 24, 2017Publication date: February 8, 2018Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventor: Kenta Matsuyama
-
Publication number: 20170194524Abstract: Provided is a solar cell that can suppress loss of power generation performance of a solar cell module when shaded and a solar cell module having the solar cell. An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: ApplicationFiled: November 30, 2016Publication date: July 6, 2017Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
-
Publication number: 20170179315Abstract: An n-type low-doped region and a first main-surface side highly doped region, which has an n-type dopant concentration higher than that in the n-type low-doped region, are provided in an n-type crystalline silicon substrate. The first main-surface side highly doped region is arranged between the n-type low-doped region and a p-type amorphous silicon layer.Type: ApplicationFiled: December 29, 2016Publication date: June 22, 2017Applicant: Panasonic Intellectual Property Management Co., Ltd.Inventors: Satoshi Tohoda, Masato Shigematsu, Kenta Matsuyama
-
Publication number: 20170005208Abstract: A method for manufacturing a solar cell may include forming a textured structure including multiple convex parts by etching a crystalline silicon substrate with etching liquid and forming an amorphous silicon layer on the crystalline silicon substrate with the textured structure formed thereon, by chemical vapor deposition or sputtering. An alkaline solution including at least one of a solution of sodium hydroxide and a solution of potassium hydroxide, additive including at least one of 4-propylbenzoic acid, 4-t-butylbenzoic acid, 4-n-butylbenzoic acid, 4-pentylbenzoic acid, 4-butoxybenzonic acid, 4-n-octylbenzenesulfonic acid, caprylic acid, and lauric acid may be added to the etching liquid. The textured structure may a chamfered section between main sloped surfaces of the convex parts, and a sharp trough part which is sandwiched by adjacent multiple convex parts.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Inventors: Kenta MATSUYAMA, Hirotada INOUE, Yasuko HIRAYAMA
-
Publication number: 20150255644Abstract: A solar cell has a texture and is equipped with an electrode formed on the texture and including flakes in addition to conductive particulates, wherein an average value of the longest axis diameters of the flakes is larger than an average value of the distances between the vertices of the texture.Type: ApplicationFiled: May 22, 2015Publication date: September 10, 2015Inventors: Yasuko HIRAYAMA, Kenta MATSUYAMA, Satoru SHIMADA
-
Publication number: 20150228816Abstract: A solar cell is provided with a semiconductor substrate upon which a textured structure that includes multiple convex parts is formed. The textured structure has chamfered sections between main sloped surfaces of the convex parts, and sharp trough parts, which are sandwiched by adjacent multiple convex parts.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Kenta MATSUYAMA, Hirotada INOUE, Yasuko HIRAYAMA
-
Publication number: 20150228814Abstract: A solar cell is provided with: a semiconductor substrate upon which a textured structure is formed; and transparent conductive layers that are formed on the substrate, the thicknesses of which are substantially fixed in a trough part of the textured structure.Type: ApplicationFiled: April 21, 2015Publication date: August 13, 2015Inventors: Kenta MATSUYAMA, Takayoshi SONE, Kazunori FUJITA