Abstract: The present disclosure provides an in-vehicle camera calibration device, a control device, and a pattern-with-a-beacon capable of performing calibration of a camera mounted on a vehicle more accurately and easily. The in-vehicle camera calibration device 100 includes a control device 110 to be mounted on a vehicle 200 and a pattern-with-a-beacon 120 to be installed outside the vehicle 200. The pattern-with-a-beacon 120 includes a calibration pattern 121 captured by the camera 201 mounted on the vehicle 200 at the time of calibration, and a beacon 122 that transmits beacon information Ib by wireless communication. The control device 110 calibrates the camera 201 based on the pattern image Gp that is the image of the calibration pattern 121 acquired from the camera 201 and the beacon information Ib received through the receiving antenna 202 mounted on the vehicle 200.

Abstract: A management system includes a plurality of resources configured to be electrically connected to an external power supply, and a management device configured to manage the resources. The management device includes a planning unit and a management unit. The planning unit is configured to determine a power balancing plan of each of the resources by using first information on a use schedule of each of the resources and second information indicating a magnitude of an environmental load in a process of generating electric power to be supplied by the external power supply. The management unit is configured to manage the resources to cause each of the resources to operate according to the power balancing plan or a modified power balancing plan in power balancing of the external power supply.

Abstract: A coordination simulation system, in which a system simulator including a plant model and a CPU simulator that controls by a microcomputer model are configured via a feedback loop, comprises a synchronization adapter that synchronizes the system simulator and the CPU simulator, wherein the synchronization adapter is provided with a function that provides alignment information per control cycle to the microcomputer model in accordance with a synchronizing signal generated in the plant model.

Abstract: A microcomputer includes a first CPU, a first bus, a first memory, a second CPU, a second bus, and a second memory. The first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding to the memories. An address translation circuit is provided. When a task so programmed to have a data area in the first memory is transferred to the second memory and executed by the second CPU, the address translation circuit carries out the following processing: the address translation circuit translates an address outputted from the second CPU so that access to the first memory by the task becomes access to the second memory. As a result, the number of access cycles is reduced and degradation in computing capability is avoided when a task is transferred between CPUs for load sharing.

Abstract: A microcomputer includes a first CPU, a first bus, a first memory, a second CPU, a second bus, and a second memory. The first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding to the memories. An address translation circuit is provided. When a task so programmed to have a data area in the first memory is transferred to the second memory and executed by the second CPU, the address translation circuit carries out the following processing: the address translation circuit translates an address outputted from the second CPU so that access to the first memory by the task becomes access to the second memory. As a result, the number of access cycles is reduced and degradation in computing capability is avoided when a task is transferred between CPUs for load sharing.

Abstract: In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.

Abstract: In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.

Abstract: The present invention provides a communication controller of a higher rate, which enables a data transfer at the maximum bus width if an inconsistency of data alignment is present, when DMA transferring a communication frame with its header and payload data into respective exclusive memory space. To achieve this, an aligner ALIGN is provided on the bus between the DMA controller and the main memory MAINMEM.