Patents by Inventor Kenta NAKAHARA
Kenta NAKAHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11977450Abstract: Backup system and method that can determine a backup destination in consideration of disaster are provided. There are provided: a data acquisition unit 110 that acquires disaster information, network information, and node information; a replication group construction unit 130 that generates, based on the disaster information, and the like, replication group information including association information between a first node that stores original data and one or more second nodes that are candidates for backup destination of the original data, and saves the replication group information in a storage unit 120; a replication destination node calculation unit 140 that, when executing backup of the original data, calculates the second node as backup destination from the replication group; and a replication processing unit 230 that replicates and stores the original data into the storage of the second node.Type: GrantFiled: August 7, 2019Date of Patent: May 7, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Takuma Tsubaki, Ryota Ishibashi, Kotaro Ono, Yuki Nakahara, Takeshi Kuwahara, Naoki Higo, Kenta Kawakami, Yusuke Urata
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Publication number: 20240136235Abstract: A method for manufacturing a substrate according to the first disclosure includes immersing a substrate on which a plurality of circuit patterns are formed in pure water or a corrosive solution, applying voltage between the plurality of circuit patterns in a state in which the substrate is immersed in the pure water or the corrosive solution and determining the substrate to be a defective product when a tree is generated in the plurality of circuit patterns due to the voltage application and determining the substrate to be a non-defective product when the tree is not generated.Type: ApplicationFiled: October 4, 2021Publication date: April 25, 2024Applicant: Mitsubishi Electric CorporationInventors: Mamoru MATSUO, Kenta NAKAHARA, Keiichi NAKAMURA
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Publication number: 20240071868Abstract: A semiconductor device includes a circuit substrate having a circuit pattern and a terminal. The terminal includes an electrode bonding portion, a main wiring portion, and a pair of sub wiring portions. The lower surface of the electrode bonding portion is bonded to the circuit pattern with a bonding material. The main wiring portion is provided upright with a side of the electrode bonding portion. The pair of sub wiring portions extending from the both ends of the main wiring portion in the width direction along sides adjacent to a side of the electrode bonding portion. The lower end portions of the pair of sub wiring portions protrude below the lower surface of the electrode bonding portion. The lower end portions of the pair of sub wiring portions are bonded to the circuit pattern together with the lower surface of the electrode bonding portion by the bonding material.Type: ApplicationFiled: March 29, 2021Publication date: February 29, 2024Applicant: Mitsubishi Electric CorporationInventor: Kenta NAKAHARA
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Patent number: 11664288Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.Type: GrantFiled: August 27, 2021Date of Patent: May 30, 2023Assignee: Mitsubishi Electric CorporationInventors: Kenta Nakahara, Akitoshi Shirao
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Publication number: 20220285243Abstract: It is an object of the present invention to improve a heat radiation property of a metal wire on a semiconductor chip in a power module. A power module includes: a plurality of metal wires connected to a surface of at least one semiconductor chip; and a thermal conductive sheet having contact with the metal wire. The metal wire includes: at least one first metal wire connecting a surface of the semiconductor chip and a circuit pattern and at least one second metal wire connecting two points on the surface of the semiconductor chip and having the same potential as the first metal wire. The thermal conductive sheet includes a graphite sheet, and a sheet surface of the thermal conductive sheet has contact with the at least one first metal wire and the at least one second metal wire.Type: ApplicationFiled: October 16, 2019Publication date: September 8, 2022Applicant: Mitsubishi Electric CorporationInventor: Kenta NAKAHARA
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Publication number: 20210391231Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.Type: ApplicationFiled: August 27, 2021Publication date: December 16, 2021Applicant: Mitsubishi Electric CorporationInventors: Kenta NAKAHARA, Akitoshi SHIRAO
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Patent number: 11195770Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.Type: GrantFiled: September 3, 2019Date of Patent: December 7, 2021Assignee: Mitsubishi Electric CorporationInventors: Kenta Nakahara, Akitoshi Shirao
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Patent number: 11171068Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.Type: GrantFiled: September 3, 2019Date of Patent: November 9, 2021Assignee: Mitsubishi Electric CorporationInventors: Kenta Nakahara, Akitoshi Shirao
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Patent number: 10971424Abstract: A power module includes a recessed base plate having a hollow portion, at least one insulating substrate disposed in the hollow portion of the base plate, at least one semiconductor chip mounted on the at least one insulating substrate, and sealing resin for sealing a surface of the hollow portion side of the base plate, the at least one insulating substrate, and the at least one semiconductor chip.Type: GrantFiled: December 4, 2018Date of Patent: April 6, 2021Assignee: Mitsubishi Electric CorporationInventors: Kenta Nakahara, Yoshihiro Yamaguchi, Fumihito Kawahara
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Patent number: 10923410Abstract: A power module includes a recessed base plate having a hollow portion, at least one insulating substrate disposed in the hollow portion of the base plate, at least one semiconductor chip mounted on the at least one insulating substrate, and sealing resin for sealing a surface of the hollow portion side of the base plate, the at least one insulating substrate, and the at least one semiconductor chip.Type: GrantFiled: December 4, 2018Date of Patent: February 16, 2021Assignee: Mitsubishi Electric CorporationInventors: Kenta Nakahara, Yoshihiro Yamaguchi, Fumihito Kawahara
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Publication number: 20200168519Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.Type: ApplicationFiled: September 3, 2019Publication date: May 28, 2020Applicant: Mitsubishi Electric CorporationInventors: Kenta NAKAHARA, Akitoshi SHIRAO
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Patent number: 10515863Abstract: According to the present invention, a power module includes an insulating substrate, a semiconductor device provided on the insulating substrate, an internal terminal provided on the insulating substrate and electrically connected to the semiconductor device, a sealing material that seals the internal terminal, the semiconductor device and the insulating substrate so that an end portion of the internal terminal is exposed, a case that is separate from the sealing material and covers the sealing material and an elastic member that connects the case and the end portion of the internal terminal.Type: GrantFiled: February 15, 2018Date of Patent: December 24, 2019Assignee: Mitsubishi Electric CorporationInventor: Kenta Nakahara
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Publication number: 20190252289Abstract: A power module includes a recessed base plate having a hollow portion, at least one insulating substrate disposed in the hollow portion of the base plate, at least one semiconductor chip mounted on the at least one insulating substrate, and sealing resin for sealing a surface of the hollow portion side of the base plate, the at least one insulating substrate, and the at least one semiconductor chip.Type: ApplicationFiled: December 4, 2018Publication date: August 15, 2019Applicant: Mitsubishi Electric CorporationInventors: Kenta NAKAHARA, Yoshihiro YAMAGUCHI, Fumihito KAWAHARA
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Patent number: 10325895Abstract: It is an object of the present invention to provide a semiconductor module in which a bonded portion has high reliability, and that has a small area. A semiconductor module includes a plurality of metal plates extending in a horizontal direction and stacked in a vertical direction, at least one switching element, and at least one circuit element. The at least one switching element is bonded between two of the plurality of metal plates, facing each other in a vertical direction. The at least one circuit element is bonded between two of the plurality of metal plates, facing each other in a vertical direction. Disposed between the plurality of metal plates is an insulating material. At least one of the plurality of metal plates is bonded to the at least one switching element and the at least one circuit element.Type: GrantFiled: March 15, 2017Date of Patent: June 18, 2019Assignee: Mitsubishi Electric CorporationInventor: Kenta Nakahara
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Publication number: 20190057914Abstract: According to the present invention, a power module includes an insulating substrate, a semiconductor device provided on the insulating substrate, an internal terminal provided on the insulating substrate and electrically connected to the semiconductor device, a sealing material that seals the internal terminal, the semiconductor device and the insulating substrate so that an end portion of the internal terminal is exposed, a case that is separate from the sealing material and covers the sealing material and an elastic member that connects the case and the end portion of the internal terminal.Type: ApplicationFiled: February 15, 2018Publication date: February 21, 2019Applicant: Mitsubishi Electric CorporationInventor: Kenta NAKAHARA
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Patent number: 10204886Abstract: A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.Type: GrantFiled: January 29, 2016Date of Patent: February 12, 2019Assignee: Mitsubishi Electric CorporationInventors: Hiroshi Yoshida, Yuji Imoto, Hidetoshi Ishibashi, Daisuke Murata, Kenta Nakahara, Seiji Oka, Junji Fujino, Nobuhiro Asaji
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Publication number: 20180294253Abstract: A semiconductor device includes semiconductor chips fixed to a board, an insulating plate having a through-hole formed therein, a first lower conductor including a lower main body formed on the lower surface of the insulating plate and soldered to any of the semiconductor chips, and a lower protrusion portion that connects with the lower main body, and extends to the outside of the insulating plate, a second lower conductor formed on a lower surface of the insulating plate and soldered to any of the semiconductor chips, an upper conductor including an upper main body formed on the upper surface of the insulating plate, and an upper protrusion portion that connects with the upper main body and extends to the outside of the insulating plate, and a connection portion provided in the through-hole and connects the upper main body and the second lower conductor.Type: ApplicationFiled: January 29, 2016Publication date: October 11, 2018Applicant: Mitsubishi Electric CorporationInventors: Hiroshi YOSHIDA, Yuji IMOTO, Hidetoshi ISHIBASHI, Daisuke MURATA, Kenta NAKAHARA, Seiji Oka, Junji FUJINO, Nobuhiro ASAJI
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Patent number: 10068819Abstract: A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.Type: GrantFiled: February 13, 2017Date of Patent: September 4, 2018Assignee: Mitsubishi Electric CorporationInventors: Seiji Oka, Hiroshi Yoshida, Hidetoshi Ishibashi, Yuji Imoto, Daisuke Murata, Kenta Nakahara
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Publication number: 20180090473Abstract: It is an object of the present invention to provide a semiconductor module in which a bonded portion has high reliability, and that has a small area. A semiconductor module includes a plurality of metal plates extending in a horizontal direction and stacked in a vertical direction, at least one switching element, and at least one circuit element. The at least one switching element is bonded between two of the plurality of metal plates, facing each other in a vertical direction. The at least one circuit element is bonded between two of the plurality of metal plates, facing each other in a vertical direction. Disposed between the plurality of metal plates is an insulating material. At least one of the plurality of metal plates is bonded to the at least one switching element and the at least one circuit element.Type: ApplicationFiled: March 15, 2017Publication date: March 29, 2018Applicant: Mitsubishi Electric CorporationInventor: Kenta NAKAHARA
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Publication number: 20170372978Abstract: A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such configuration makes it possible to reduce a resistance in a current path while preventing the problems occurring when the external electrode is soldered on the semiconductor chip.Type: ApplicationFiled: February 13, 2017Publication date: December 28, 2017Applicant: Mitsubishi Electric CorporationInventors: Seiji OKA, Hiroshi YOSHIDA, Hidetoshi ISHIBASHI, Yuji IMOTO, Daisuke MURATA, Kenta NAKAHARA