Patents by Inventor Kenta ONO

Kenta ONO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11151321
    Abstract: A method, a structure, and a computer system for resolving an anaphora. The exemplary embodiments may include extracting individual context data from an individual expression and determining whether the individual expression includes an anaphora representation based on the individual context data. The exemplary embodiments may further include, based on determining that the individual expression includes the anaphora representation, extracting anaphora context data and identifying an object of one or more objects to which the anaphora representation refers based on comparing the individual context data and the anaphora context data to data detailing the one or more objects.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Shunsuke Ishikawa, Yasuyuki Tominaga, Hiroaki Uetsuki, Asako Ono, Tohru Hasegawa, Kenta Watanabe
  • Publication number: 20210233778
    Abstract: An etching method includes forming a film on a surface of a substrate having a region to be etched and a mask. The mask is provided on the region and includes an opening that partially exposes the region. The film is made of the same material as that of the region. The etching method further includes etching the region.
    Type: Application
    Filed: January 28, 2021
    Publication date: July 29, 2021
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Maju TOMURA, Tomohiko NIIZEKI, Takayuki KATSUNUMA, Hironari SASAGAWA, Yuta NAKANE, Shinya ISHIKAWA, Kenta ONO, Sho KUMAKURA, Yusuke TAKINO, Masanobu HONDA
  • Publication number: 20210202260
    Abstract: A technique enables etching of a film on a substrate with reduced etching on the surface of a side wall. An etching method includes forming a protective layer on a surface of aside wall defining a recess in a substrate. The protective layer contains sulfur atoms. The etching method further includes etching a film on the substrate to increase a depth of the recess after forming the protective layer.
    Type: Application
    Filed: November 19, 2020
    Publication date: July 1, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shinya ISHIKAWA, Kenta ONO, Masanobu HONDA
  • Publication number: 20210193477
    Abstract: A system, apparatus and method enable etching of a layer of a substrate with reduced etching on the surface of a side wall of the layer. The etching method includes forming a protective layer on a surface of the side wall defining a recess in the layer. The protective layer contains phosphorus. The etching method further includes etching the layer in one or more additional cycles so as to increase a depth of the recess after the forming the protective layer.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 24, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shinya ISHIKAWA, Kenta ONO, Maju TOMURA, Masanobu HONDA
  • Patent number: 8697546
    Abstract: A method of manufacturing a semiconductor device, comprising bonding a first principal surface of a substrate to a supporting substrate through a light-to-heat conversion film, and removing a portion of the light-to-heat conversion film exposed on the supporting substrate. A method of manufacturing a semiconductor device, comprising forming a light-to-heat conversion film on a supporting substrate, bonding a semiconductor substrate to the supporting substrate, so that the light-to-heat conversion film extends outside the semiconductor substrate, performing an anti-contamination treatment on the light-to-heat conversion film, and separating the supporting substrate and the semiconductor substrate from each other.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: April 15, 2014
    Inventor: Kenta Ono
  • Patent number: 8582277
    Abstract: A multilayer ceramic electronic component comprising an element body in which a dielectric layer and an internal electrode layer are stacked. The dielectric layer is constituted from a dielectric ceramic composition including; a compound having a perovskite structure expressed by a formula of ABO3 (A is at least one selected from Ba, Ca, and Sr; B is at least one selected from Ti, Zr, and Hf); an oxide of Mg; an oxide of rare earth elements including Sc and Y; and an oxide including Si. The dielectric ceramic composition comprises a plurality of dielectric particles and a grain boundary present in between the dielectric particles. In the grain boundary, when content ratios of Mg and Si are set to D(Mg) and D(Si) respectively, D(Mg) is 0.2 to 1.8 wt % in terms of MgO, and D(Si) is 0.4 to 8.0 wt % in terms of SiO2.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: November 12, 2013
    Assignee: TDK Corporation
    Inventors: Hirobumi Tanaka, Makoto Endo, Satoko Ueda, Daisuke Ueda, Shogo Murosawa, Daisuke Yoshida, Kenta Ono, Minoru Ogasawara, Tatsuya Kikuchi
  • Publication number: 20120295415
    Abstract: A method of manufacturing a semiconductor device, comprising bonding a first principal surface of a substrate to a supporting substrate through a light-to-heat conversion film, and removing a portion of the light-to-heat conversion film exposed on the supporting substrate. A method of manufacturing a semiconductor device, comprising forming a light-to-heat conversion film on a supporting substrate, bonding a semiconductor substrate to the supporting substrate, so that the light-to-heat conversion film extends outside the semiconductor substrate, performing an anti-contamination treatment on the light-to-heat conversion film, and separating the supporting substrate and the semiconductor substrate from each other.
    Type: Application
    Filed: May 1, 2012
    Publication date: November 22, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Kenta ONO
  • Publication number: 20120162858
    Abstract: A multilayer ceramic electronic component comprising an element body in which a dielectric layer and an internal electrode layer are stacked. The dielectric layer is constituted from a dielectric ceramic composition including; a compound having a perovskite structure expressed by a formula of ABO3 (A is at least one selected from Ba, Ca, and Sr; B is at least one selected from Ti, Zr, and Hf); an oxide of Mg; an oxide of rare earth elements including Sc and Y; and an oxide including Si. The dielectric ceramic composition comprises a plurality of dielectric particles and a grain boundary present in between the dielectric particles. In the grain boundary, when content ratios of Mg and Si are set to D(Mg) and D(Si) respectively, D(Mg) is 0.2 to 1.8 wt % in terms of MgO, and D(Si) is 0.4 to 8.0 wt % in terms of SiO2.
    Type: Application
    Filed: November 21, 2011
    Publication date: June 28, 2012
    Applicant: TDK CORPORATION
    Inventors: Hirobumi TANAKA, Makoto ENDO, Satoko UEDA, Daisuke UEDA, Shogo MUROSAWA, Daisuke YOSHIDA, Kenta ONO, Minoru OGASAWARA, Tatsuya KIKUCHI