Abstract: The video signal processing method of this invention is employed in a video signal processing apparatus that includes a plurality of signal processing parts, each for executing signal processing, for processing two or more digitalized video signals in parallel, and the video signal processing method includes the steps of selecting one or more video signals from the two or more digitalized video signals; and obtaining an object video signal by selecting, from the plurality of signal processing parts, signal processing parts used for signal processing of the selected video signals in accordance with a mode of the object video signal and executing the signal processing in the selected signal processing parts in an order in accordance with the mode of the object video signal.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: The video signal processing method of this invention is employed in a video signal processing apparatus that includes a plurality of signal processing parts, each for executing signal processing, for processing two or more digitalized video signals in parallel, and the video signal processing method includes the steps of selecting one or more video signals from the two or more digitalized video signals; and obtaining an object video signal by selecting, from the plurality of signal processing parts, signal processing parts used for signal processing of the selected video signals in accordance with a mode of the object video signal and executing the signal processing in the selected signal processing parts in an order in accordance with the mode of the object video signal.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: The decrypting device of this invention includes: a decrypting key generation circuit for generating a decrypting key based on first decrypting key information and second decrypting key information; and a decrypting circuit for decrypting encrypted information using the decrypting key, wherein the first decrypting key information is input from outside the decrypting device, and the second decrypting key information is stored inside the decrypting device.

Abstract: The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single part memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A television receiver (a signal processing apparatus) equipped with a microprocessor unit, wherein a high speed processing, such as video decoding, is performed by a programmable operation circuit, and a low speed processing, such as control processing, synchronous processing, or deflection processing, is performed by the microprocessor unit.

Abstract: A contour restoration apparatus has a plurality of delay circuits connected in series. Maximum and minimum value detection circuits detect maximum and minimum values among an input video signal and output signals of the delay circuits. A mean value circuit is used to calculate a mean value of the of the maximum and minimum values. The mean value is subtracted from a delayed signal having a delay time of one-half of a delay time obtained from all the delay circuits. An adder is used to add the result of the subtraction to the delayed signal. A non-linear processing circuit processes the output of said adder and the maximum and minimum values. The non-linear circuit outputs the output signal of the adder, if the output signal of said adder is between the maximum value and the minimum value. A contour extraction circuit multiplies a signal located centrally among the input video signal, the output signals and the signals located before and after the input signal with a predetermined coefficient.

Abstract: A contour restoration circuit comprises an input terminal, a plural of delay circuits connected to the input terminal in series, a maximum value detection circuit, a minimum value detection circuit, a mean value calculating the mean value from the maximum and minimum values, a subtractor for subtracting the mean value from the input video signal, a gain controller for the subtracted signal, an adder for adding the gain controlled signal to the input video signal and an output terminal.

Abstract: In the NTSC color television system, a signal having a medium level in the three signals of the bands the color sub-carrier frequency of neighboring three scanning lines is substracted from the signal of the central scanning line of the three scanning lines, the resultant signal is a luminance signal containing no cross luminance, even if the composite video signal in the three scanning lines does not maintain vertical correlation.

Abstract: A device detects a correlation between frames represented by a video signal of an interlaced scanning format. A sudden motion of an object represented by the video signal is detected on the basis of the detected correlation. A normal motion of the object represented by the video signal is detected on the basis of the detected correlation. Scanning lines represented by the video signl are interpolated with changeable interpolation characteristics. The interpolation characteristics are changed in response to the detected normal motion of the object. The interpolation characteristics are changed in response to the detected sudden motion of the object.