Patents by Inventor Kenta Uchiyama
Kenta Uchiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9899304Abstract: A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.Type: GrantFiled: December 16, 2016Date of Patent: February 20, 2018Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Imafuji, Keiji Yoshizawa, Hirokazu Yoshino, Kenta Uchiyama
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Publication number: 20170186677Abstract: A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.Type: ApplicationFiled: December 16, 2016Publication date: June 29, 2017Inventors: KEI IMAFUJI, KEIJI YOSHIZAWA, HIROKAZU YOSHINO, KENTA UCHIYAMA
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Patent number: 9515050Abstract: A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode.Type: GrantFiled: June 16, 2014Date of Patent: December 6, 2016Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kenta Uchiyama, Akihiko Tateiwa
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Patent number: 9136220Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed on the first surface of the first sealing insulating layer, at least one insulating layer formed on the at least one wiring layer, a second semiconductor chip mounted on the at least one insulating layer, and a second sealing insulating layer formed on the at least one insulating layer and configured to seal the second semiconductor chip.Type: GrantFiled: September 10, 2012Date of Patent: September 15, 2015Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kenta Uchiyama
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Patent number: 9099478Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed on the first surface of the first sealing insulating layer, at least one insulating layer formed on the at least one wiring layer, a second semiconductor chip mounted on the at least one insulating layer, and a second sealing insulating layer formed on the at least one insulating layer and configured to seal the second semiconductor chip.Type: GrantFiled: September 10, 2012Date of Patent: August 4, 2015Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kenta Uchiyama
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Patent number: 9041211Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip.Type: GrantFiled: September 6, 2012Date of Patent: May 26, 2015Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kenta Uchiyama
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Publication number: 20140291865Abstract: A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode.Type: ApplicationFiled: June 16, 2014Publication date: October 2, 2014Inventors: Kenta UCHIYAMA, Akihiko Tateiwa
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Patent number: 8786103Abstract: A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode.Type: GrantFiled: April 7, 2010Date of Patent: July 22, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kenta Uchiyama, Akihiko Tateiwa
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Patent number: 8692363Abstract: A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.Type: GrantFiled: November 14, 2011Date of Patent: April 8, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Naoyuki Koizumi, Masahiro Kyozuka, Kenta Uchiyama
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Patent number: 8450853Abstract: A semiconductor device includes an electronic component having an electrode pad provided on an electrode pad forming face, and a rear face positioned on a side opposite to the electrode pad forming face; an insulating member provided to seal a periphery of the electronic component, and having a first face exposing the electrode pad forming face of the electronic component and a second face exposing the rear face of the electronic component; a multi-layer wiring structure body provided to cover the first face of the insulating member, the electrode pad, and the electrode pad forming face, and including a plurality of insulating layers laminated on each other, and a wiring pattern; and a piercing electrode piercing the insulating member from the first face to the second face. The wiring pattern is directly connected to the electrode pad and the piercing electrode.Type: GrantFiled: February 17, 2010Date of Patent: May 28, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Kenta Uchiyama
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Publication number: 20130069219Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and configured to seal the target circuit surface and the side surface, at least one wiring layer formed on the first surface of the first sealing insulating layer, at least one insulating layer formed on the at least one wiring layer, a second semiconductor chip mounted on the at least one insulating layer, and a second sealing insulating layer formed on the at least one insulating layer and configured to seal the second semiconductor chip.Type: ApplicationFiled: September 10, 2012Publication date: March 21, 2013Inventor: Kenta UCHIYAMA
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Publication number: 20130069245Abstract: A semiconductor package includes a first semiconductor chip including a target circuit surface and a side surface, a first sealing insulating layer including a first surface positioned toward the target circuit surface and a second surface positioned opposite to the first surface, the first sealing insulating layer sealing the target circuit surface and the side surface, a wiring layer formed on the first surface of the first sealing insulating layer, an insulating layer formed on the wiring layer, a second semiconductor chip mounted on the second surface of the first sealing insulating layer, and a second sealing insulating layer formed on the second surface and sealing the second semiconductor chip.Type: ApplicationFiled: September 6, 2012Publication date: March 21, 2013Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kenta UCHIYAMA
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Patent number: 8314347Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.Type: GrantFiled: December 14, 2009Date of Patent: November 20, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kenta Uchiyama, Akihiko Tateiwa, Yuji Kunimoto
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Publication number: 20120119379Abstract: A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Naoyuki KOIZUMI, Masahiro Kyozuka, Kenta Uchiyama
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Publication number: 20120119391Abstract: A semiconductor package includes a support member having a concave portion formed in one surface thereof. A semiconductor chip is accommodated in the concave portion so that a circuit formation surface of the semiconductor chip is exposed on a side of the one surface of the support member. A wiring structure including a wiring layer electrically connected to the semiconductor chip is formed on the circuit formation surface of the semiconductor chip and the one surface of the support member. A portion of the support member including the one surface is made of silicon or borosilicate glass.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Naoyuki KOIZUMI, Kenta Uchiyama
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Patent number: 8174109Abstract: An electronic device includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first electronic component, a first sealing resin, and a first multilayer interconnection structure including a first interconnection pattern directly connected to a first electrode pad of the first electronic component. The second semiconductor device includes a second electronic component, a second sealing resin, and a second multilayer interconnection structure including a second interconnection pattern directly connected to a second electrode pad of the second electronic component. The first semiconductor device is stacked on and bonded to the second semiconductor device through an adhesive layer with the first multilayer interconnection structure of the first semiconductor device facing toward the second sealing resin of the second semiconductor device.Type: GrantFiled: April 2, 2010Date of Patent: May 8, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventor: Kenta Uchiyama
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Patent number: 8169072Abstract: A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode.Type: GrantFiled: March 29, 2010Date of Patent: May 1, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kenta Uchiyama, Akihiko Tateiwa
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Publication number: 20100258944Abstract: A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode.Type: ApplicationFiled: April 7, 2010Publication date: October 14, 2010Inventors: Kenta Uchiyama, Akihiko Tateiwa
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Publication number: 20100258946Abstract: A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode.Type: ApplicationFiled: March 29, 2010Publication date: October 14, 2010Inventors: Kenta UCHIYAMA, Akihiko Tateiwa
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Publication number: 20100252937Abstract: An electronic device includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first electronic component, a first sealing resin, and a first multilayer interconnection structure including a first interconnection pattern directly connected to a first electrode pad of the first electronic component. The second semiconductor device includes a second electronic component, a second sealing resin, and a second multilayer interconnection structure including a second interconnection pattern directly connected to a second electrode pad of the second electronic component. The first semiconductor device is stacked on and bonded to the second semiconductor device through an adhesive layer with the first multilayer interconnection structure of the first semiconductor device facing toward the second sealing resin of the second semiconductor device.Type: ApplicationFiled: April 2, 2010Publication date: October 7, 2010Inventor: Kenta UCHIYAMA