Patents by Inventor Kenta Yamamukai

Kenta Yamamukai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor device
    Patent number: 6930003
    Abstract: A method of manufacturing a semiconductor device includes a memory region in which non-volatile memory devices are arranged in a matrix form of a plurality of rows and a plurality of columns to form a memory cell array, the method of manufacturing a semiconductor device including the steps of: forming a gate insulation layer above a semiconductor layer; forming a first conductive layer and a stopper layer having a predetermined pattern above the gate insulation layer; forming a first insulation layer and a second conductive layer over the entire surface of the memory region; forming a first side-wall conductive layer on each of both side surfaces of the first conductive layer, and on the semiconductor layer with the first insulation layer interposed, by anisotropic etching of that second conductive layer; forming a third conductive layer over the entire surface of the memory region; forming a second side-wall conductive layer on each of both side surfaces of the first conductive layer, and on the semiconducto
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: August 16, 2005
    Assignee: Seiko Epson Corporation
    Inventor: Kenta Yamamukai
  • Method of manufacturing semiconductor device
    Publication number: 20040097035
    Abstract: A method of manufacturing a semiconductor device includes a memory region in which non-volatile memory devices are arranged in a matrix form of a plurality of rows and a plurality of columns to form a memory cell array, the method of manufacturing a semiconductor device including the steps of: forming a gate insulation layer above a semiconductor layer; forming a first conductive layer and a stopper layer having a predetermined pattern above the gate insulation layer; forming a first insulation layer and a second conductive layer over the entire surface of the memory region; forming a first side-wall conductive layer on each of both side surfaces of the first conductive layer, and on the semiconductor layer with the first insulation layer interposed, by anisotropic etching of that second conductive layer; forming a third conductive layer over the entire surface of the memory region; forming a second side-wall conductive layer on each of both side surfaces of the first conductive layer, and on the semiconducto
    Type: Application
    Filed: August 8, 2003
    Publication date: May 20, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Kenta Yamamukai