Patents by Inventor Kenta Yoshinaga
Kenta Yoshinaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934986Abstract: Provided are an index value calculator to calculate an index value obtained by quantifying a degree of status for evaluation items, a teamwork evaluator to evaluate a teamwork based on the index value, a support content determiner to select target persons to be supported including the members of the team based on the evaluation result of the teamwork and determine support contents in accordance with the target persons to be supported, and a presentation information generator to generate presentation information for presenting the determined support contents for each of the output devices corresponding to the selected target persons to be supported, and the teamwork evaluator evaluates the teamwork using an evaluation logic configured by combining logical formulas for comparing a threshold value set for evaluation items with the calculated index value.Type: GrantFiled: March 23, 2020Date of Patent: March 19, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenta Fukami, Mami Naruse, Mitsunobu Yoshinaga, Nami Yamamoto
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Patent number: 10790229Abstract: A semiconductor memory device according to an embodiment includes a substrate; a plate-like first conductivity layer provided above the substrate and extending parallel to a substrate plane to bestride first and second regions; a plate-like second conductivity layer provided above the first conductivity layer to be separated from the first conductivity layer, an end portion of the first conductivity layer has a protruding staircase shape in the first region, the second conductivity layer extending parallel to the first conductivity layer to bestride the first and second regions; a first contact connected to the first conductivity layer at a side surface or a bottom surface of the first conductivity layer and extending from the first conductivity layer toward the substrate, the first contact being connected at a position where the end portion of the first conductivity layer in the first region protrudes, and a diameter size of a portion of the first contact connected at a side surface or a bottom surface of thType: GrantFiled: August 29, 2018Date of Patent: September 29, 2020Assignee: Toshiba Memory CorporationInventors: Kenta Yoshinaga, Hideki Inokuma, Hisashi Kato, Masakazu Sawano
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Patent number: 10483124Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.Type: GrantFiled: September 10, 2018Date of Patent: November 19, 2019Assignee: Toshiba Memory CorporationInventors: Masakazu Sawano, Takahiro Tomimatsu, Junichi Shibata, Hideki Inokuma, Hisashi Kato, Kenta Yoshinaga
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Publication number: 20190287903Abstract: A semiconductor memory device according to an embodiment includes a substrate; a plate-like first conductivity layer provided above the substrate and extending parallel to a substrate plane to bestride first and second regions; a plate-like second conductivity layer provided above the first conductivity layer to be separated from the first conductivity layer, an end portion of the first conductivity layer has a protruding staircase shape in the first region, the second conductivity layer extending parallel to the first conductivity layer to bestride the first and second regions; a first contact connected to the first conductivity layer at a side surface or a bottom surface of the first conductivity layer and extending from the first conductivity layer toward the substrate, the first contact being connected at a position where the end portion of the first conductivity layer in the first region protrudes, and a diameter size of a portion of the first contact connected at a side surface or a bottom surface of thType: ApplicationFiled: August 29, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Kenta Yoshinaga, Hideki Inokuma, Hisashi Kato, Masakazu Sawano
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Publication number: 20190214268Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.Type: ApplicationFiled: September 10, 2018Publication date: July 11, 2019Applicant: Toshiba Memory CorporationInventors: Masakazu SAWANO, Takahiro TOMIMATSU, Junichi SHIBATA, Hideki INOKUMA, Hisashi KATO, Kenta YOSHINAGA
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Publication number: 20120100641Abstract: According to an embodiment, an etching apparatus includes a reaction chamber, a vacuum pump connected to the reaction chamber through the gate valve, a holding unit which holds a processing subject, an etching gas supply unit, a heating unit, and a sublimation amount determining unit. The etching gas supply unit supplies an etching gas which forms a reaction product by reacting with the processing subject to the reaction chamber. The heating unit heats the processing subject to an equal or higher temperature than temperature at which the reaction product will be sublimated. The sublimation amount determining unit monitors a predetermined physical amount which changes depending on the degree of sublimation of the reaction product during the sublimation process using the heating unit, in which the physical amount is used as a sublimation-amount-dependent change value which changes over time.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Katsuhiko TACHIBANA, Kenta Yoshinaga