Patents by Inventor Kentaro Chikamatsu

Kentaro Chikamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10700188
    Abstract: A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 30, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Kentaro Chikamatsu
  • Publication number: 20200176400
    Abstract: A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Inventors: Kentaro CHIKAMATSU, Koshun SAITO, Kenichi YOSHIMOCHI
  • Publication number: 20200176595
    Abstract: There is provided a nitride semiconductor device that includes a first nitride semiconductor layer configured as an electron transit layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and configured as an electron supply layer, a ridge-shaped nitride semiconductor gate layer disposed on the second nitride semiconductor layer and including an acceptor-type impurity, and a gate electrode formed on the nitride semiconductor gate layer. The gate electrode includes a first metal film that is formed on the nitride semiconductor gate layer and is mainly made of Ti, and a second metal film that is formed on the first metal film and is made of TiN.
    Type: Application
    Filed: November 29, 2019
    Publication date: June 4, 2020
    Inventors: Hirotaka OTAKE, Shinya Takado, Kentaro Chikamatsu
  • Patent number: 10600744
    Abstract: A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 24, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kentaro Chikamatsu, Koshun Saito, Kenichi Yoshimochi
  • Publication number: 20190140086
    Abstract: A semiconductor device is provided with, a group-III nitride semiconductor layered structure that includes a heterojunction, an insulating layer which has a gate opening that reaches the group-III nitride semiconductor layered structure and which is disposed on the group-III nitride semiconductor layered structure, a gate insulating film that covers the bottom and the side of the gate opening, a gate electrode defined on the gate insulating film inside the gate opening, a source electrode and a drain electrode which are disposed to be spaced apart from the gate electrode so as to sandwich the gate electrode, a first conductive layer embedded in the insulating layer between the gate electrode and the drain electrode, and a second conductive layer that is embedded in the insulating layer above the first conductive layer in a region closer to the drain electrode side than the first conductive layer.
    Type: Application
    Filed: November 1, 2018
    Publication date: May 9, 2019
    Inventor: Kentaro CHIKAMATSU
  • Publication number: 20180138134
    Abstract: A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin.
    Type: Application
    Filed: November 2, 2017
    Publication date: May 17, 2018
    Inventors: Kentaro CHIKAMATSU, Koshun SAITO, Kenichi YOSHIMOCHI
  • Patent number: 9729135
    Abstract: In a gate driver for driving a first transistor, the gate driver includes first, second and third push-pull circuits, in each of the push-pull circuits, two transistors are connected in series, an output terminal of the first push-pull circuit is connected to the gate of the first transistor, an output terminal of the second push-pull circuit is connected to the gate of a second transistor included in the first push-pull circuit and an output terminal of the third push-pull circuit is connected to the gate of a third transistor included in the first push-pull circuit.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 8, 2017
    Assignees: Rohm Co., Ltd., Kyoto University
    Inventors: Atsushi Yamaguchi, Kentaro Chikamatsu, Takashi Hikihara, Kohei Nagaoka
  • Patent number: 9704982
    Abstract: A semiconductor device comprises a Group III nitride semiconductor lamination structure including a hetero-junction; an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure; a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion; a gate electrode formed on the gate insulating film in the gate opening portion; a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: July 11, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Kentaro Chikamatsu, Taketoshi Tanaka, Minoru Akutsu
  • Publication number: 20160218203
    Abstract: A semiconductor device comprises a Group III nitride semiconductor lamination structure including a hetero-junction; an insulating layer formed on the Group III nitride semiconductor lamination structure, the insulating layer including a gate opening portion extending to the Group III nitride semiconductor lamination structure; a gate insulating film configured to cover a bottom portion and a side portion of the gate opening portion; a gate electrode formed on the gate insulating film in the gate opening portion; a source electrode and a drain electrode disposed in a spaced-apart relationship with the gate electrode to sandwich the gate electrode and electrically connected to the Group III nitride semiconductor lamination structure; and a conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and insulated from the gate electrode by the gate insulating film, the conductive layer electrically connected to the source electrode.
    Type: Application
    Filed: January 21, 2016
    Publication date: July 28, 2016
    Applicant: ROHM CO., LTD.
    Inventors: Kentaro CHIKAMATSU, Taketoshi TANAKA, Minoru AKUTSU
  • Publication number: 20160087623
    Abstract: In a gate driver for driving a first transistor, the gate driver includes first, second and third push-pull circuits, in each of the push-pull circuits, two transistors are connected in series, an output terminal of the first push-pull circuit is connected to the gate of the first transistor, an output terminal of the second push-pull circuit is connected to the gate of a second transistor included in the first push-pull circuit and an output terminal of the third push-pull circuit is connected to the gate of a third transistor included in the first push-pull circuit.
    Type: Application
    Filed: September 21, 2015
    Publication date: March 24, 2016
    Inventors: Atsushi Yamaguchi, Kentaro Chikamatsu, Takashi Hikihara, Kohei Nagaoka
  • Patent number: 8093627
    Abstract: This nitride semiconductor device comprises: an n-type first layer made of a group III nitride semiconductor; a p-type second layer made of a group III nitride semiconductor layer provided on the first layer; and an n-type third layer made of a group III nitride semiconductor with a p-type impurity content of not more than 1×1018 cm?3 provided on the second layer.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: January 10, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Hirotaka Otake, Kentaro Chikamatsu
  • Publication number: 20090179227
    Abstract: This nitride semiconductor device comprises: an n-type first layer made of a group III nitride semiconductor; a p-type second layer made of a group III nitride semiconductor layer provided on the first layer; and an n-type third layer made of a group III nitride semiconductor with a p-type impurity content of not more than 1×1018 cm?3 provided on the second layer.
    Type: Application
    Filed: December 26, 2008
    Publication date: July 16, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Hirotaka OTAKE, Kentaro Chikamatsu
  • Patent number: D832227
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: October 30, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Kentaro Chikamatsu, Koshun Saito, Kenichi Yoshimochi
  • Patent number: D832228
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: October 30, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Kentaro Chikamatsu, Koshun Saito, Kenichi Yoshimochi