Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.

Abstract: A charge transfer path of a transfer transistor constituted by a vertical transistor is reduced. An imaging element includes a photoelectric conversion unit, a charge holding unit, a charge transfer unit, and an image signal generation unit. The photoelectric conversion unit is disposed on a semiconductor substrate and generates charge corresponding to incident light by photoelectric conversion. The charge holding unit holds the charge. The charge transfer unit includes an opening portion, which is formed in the semiconductor substrate and having a polygonal shape in a plan view, and an embedded gate disposed in the opening portion and transfers the charge from the photoelectric conversion unit to the charge holding unit. The image signal generation unit generates an image signal based on the held charge.

Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.

Abstract: According to one embodiment, an imaging device includes a semiconductor layer, an electrode, first and second insulating films, and a light blocking film. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface, and includes pixels configured to detect light. The electrode is provided on the first surface and is configured to control an output of the pixels. The first insulating film is provided on the second surface. The second insulating film is provided on the first insulating film and has a smaller refractive index in a visible light range than the first insulating film. One end of the light blocking film is located in the second insulating film or at a same level as a surface of the second insulating film. Another end of the light blocking film is located in the semiconductor layer.

Abstract: A solid-state imaging device includes a plurality of photoelectric transducers disposed in an array in a semiconductor layer. Each photoelectric transducer includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type. The first and second regions are in direct contact. An isolation region is between each adjacent pair of photoelectric transducers. The isolation region includes an insulating material extending from a surface of the semiconductor layer and a third semiconductor region of the first conductivity type surrounding the insulating material. The third semiconductor region is between the insulating material and the first semiconductor region, and the first semiconductor region is between the second and third semiconductor regions.

Abstract: According to one embodiment, an imaging device includes a semiconductor layer, an electrode, first and second insulating films, and a light blocking film. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface, and includes pixels configured to detect light. The electrode is provided on the first surface and is configured to control an output of the pixels. The first insulating film is provided on the second surface. The second insulating film is provided on the first insulating film and has a smaller refractive index in a visible light range than the first insulating film. One end of the light blocking film is located in the second insulating film or at a same level as a surface of the second insulating film. Another end of the light blocking film is located in the semiconductor layer.

Abstract: A semiconductor device includes a semiconductor wafer, a source region and a drain region formed within the semiconductor wafer, a gate electrode formed on the semiconductor wafer between the source region and the drain region, an interlayer film formed on the semiconductor wafer and the gate electrode, and a dummy floating pattern embedded into the interlayer film, having a film containing metal or a metallic compound having tensile stress or compressive stress and formed to be spaced from the semiconductor wafer and the gate electrode.

Abstract: A buried insulating layer is buried at a position lower than a surface of a semiconductor substrate, and a cap insulating layer, which is made of a material different from the buried insulating layer, is formed on the buried insulating layer not to protrude into a shoulder portion of a step between the semiconductor substrate and the buried insulating layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first region including an n-type active element and a second region including a p-type active element, an element isolation region isolating plurality of the n-type active element and plurality of the p-type active element, a first insulating film having a tensile stress provided on the first region and on the element isolation regions of the second regions, and a second insulating film having a compression stress provided on the second region.

Abstract: A semiconductor device includes a semiconductor wafer, a source region and a drain region formed within the semiconductor wafer, a gate electrode formed on the semiconductor wafer between the source region and the drain region, an interlayer film formed on the semiconductor wafer and the gate electrode, and a dummy floating pattern embedded into the interlayer film, having a film containing metal or a metallic compound having tensile stress or compressive stress and formed to be spaced from the semiconductor wafer and the gate electrode.

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate and defining a device region. A MOSFET includes a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and a source/drain diffusion area sandwiching a channel region below the gate electrode. A stress film is continuously formed over the gate electrode and source/drain diffusion area and in the trench and applies a tensile stress or compressive stress to the semiconductor substrate. An insulating film buries the trench via the stress film.